ATA6602-PLQW ATMEL [ATMEL Corporation], ATA6602-PLQW Datasheet - Page 65

• Manufacturer Part Number: ATA6602-PLQW
• Description: Microcontroller with LIN Transceiver, 5V Regulator and Watchdog
• Manufacturer: ATMEL [ATMEL Corporation]

4.7.8.6
4.7.8.7
4.8
4.8.1
4921C–AUTO–01/07
System Control and Reset
Resetting the AVR
Port Pins
On-chip Debug System
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important is then to ensure that no pins drive resistive loads. In sleep modes where both
the I/O clock (clk
be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section
which pins are enabled. If the input buffer is enabled and the input signal is left floating or have
an analog signal level close to V
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and
DIDR0). Refer to
able Register 0 – DIDR0” on page 278
If the On-chip debug system is enabled by the DWEN Fuse and the chip enters sleep mode, the
main clock source is enabled and hence always consumes power. In the deeper sleep modes,
this will contribute significantly to the total current consumption.
During reset, all I/O Registers are set to their initial values, and the program starts execution
from the Reset Vector. For the ATA6603, the instruction placed at the Reset Vector must be a
JMP – Absolute Jump – instruction to the reset handling routine. For the ATA6602, the instruc-
tion placed at the Reset Vector must be an RJMP – Relative Jump – instruction to the reset
handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not
used, and regular program code can be placed at these locations. This is also the case if the
Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or
vice versa (ATA6602/ATA6603 only). The circuit diagram in
reset logic.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The time-out
period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-
ferent selections for the delay period are presented in
Table 4-20 on page 67
CC
I/O
“Digital Input Disable Register 1 – DIDR1” on page 261
/2 on an input pin can cause significant current even in active mode. Digital
) and the ADC clock (clk
“Digital Input Enable and Sleep Modes” on page 91
CC
/2, the input buffer will use excessive power.
defines the electrical parameters of the reset circuitry.
for details.
ADC
) are stopped, the input buffers of the device will
“Clock Sources” on page
ATA6602/ATA6603
Figure 4-15 on page 66
and
“Digital Input Dis-
49.
for details on
shows the
65