ATA6602-PLQW ATMEL [ATMEL Corporation], ATA6602-PLQW Datasheet - Page 256

• Manufacturer Part Number: ATA6602-PLQW
• Description: Microcontroller with LIN Transceiver, 5V Regulator and Watchdog
• Manufacturer: ATMEL [ATMEL Corporation]

4.19.8.5
Table 4-94.
256
Status Code
(TWSR)
Prescaler Bits
are 0
0xF8
0x00
ATA6602/ATA6603
Miscellaneous States
Status of the 2-wire Serial
Bus and 2-wire Serial
Interface Hardware
No relevant state information
available; TWINT = “0”
Bus error due to an illegal
START or STOP condition
Miscellaneous States
Figure 4-95. Formats and States in the Slave Transmitter Mode
There are two status codes that do not correspond to a defined TWI state (see
Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not
set. This occurs between other states, and when the TWI is not involved in a serial transfer.
Status 0x00 indicates that a bus error has occurred during a 2-wire Serial Bus transfer. A bus
error occurs when a START or STOP condition occurs at an illegal position in the format frame.
Examples of such illegal positions are during the serial transfer of an address byte, a data byte,
or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the
TWSTO Flag must set and TWINT must be cleared by writing a logic one to it. This causes the
TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in
TWCR are affected). The SDA and SCL lines are released, and no STOP condition is
transmitted.
Reception of the own
slave address and one or
more data bytes
Arbitration lost as master
and addressed as slave
Last data byte transmitted.
Switched to not addressed
slave (TWEA = '0')
No TWDR action
No TWDR action
To/from TWDR
From master to slave
From slave to master
Application Software Response
S
STA
SLA
0
No TWCR action
STO
1
To TWCR
R
DATA
TWINT TWEA
$A8
$B0
A
A
1
n
A
X
DATA
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the 2-Wire Serial Bus. The
prescaler bits are zero or masked to zero
Next Action Taken by TWI Hardware
Wait or proceed current transfer
Only the internal hardware is affected, no STOP
condition is sent on the bus. In all cases, the bus
is released and TWSTO is cleared.
$B8
A
DATA
$C0
$C8
A
A
Table
4921C–AUTO–01/07
P or S
All 1's
4-94).
P or S