C8051F540-TB Silicon Laboratories Inc, C8051F540-TB Datasheet - Page 159

BOARD PROTOTYPE W/C8051F540

C8051F540-TB

Manufacturer Part Number
C8051F540-TB
Description
BOARD PROTOTYPE W/C8051F540
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F540-TB

Contents
Board
Processor To Be Evaluated
C8051F54x
Processor Series
C8051F54x
Interface Type
USB
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F54x
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1672
SFR Definition 18.8. P2MASK: Port 2 Mask Register
SFR Address = 0xB2; SFR Page = 0x00
SFR Definition 18.9. P2MAT: Port 2 Match Register
SFR Address = 0xB1; SFR Page = 0x00
Note: Ports 2.2-P2.7 only available on 32-pin packages.
Note: Ports 2.2-P2.7 only available on 32-pin packages.
Name
Reset
Name
Reset
Bit
7:0
Bit
7:0
Type
Type
Bit
Bit
P2MASK[7:0]
P2MAT[7:0]
Name
Name
7
0
7
1
Port 2 Mask Value.
Selects P2 pins to be compared to the corresponding bits in P2MAT.
0: P2.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P2.n pin logic value is compared to P2MAT.n.
Port 2 Match Value.
Match comparison value used on Port 2 for bits in P2MAT which are set to 1.
0: P2.n pin logic value is compared with logic LOW.
1: P2.n pin logic value is compared with logic HIGH.
6
0
6
1
5
0
5
1
Rev. 1.1
P2MASK[7:0]
4
0
4
1
P2MAT[7:0]
R/W
R/W
Function
Function
3
0
3
1
2
0
2
1
C8051F54x
1
0
1
1
0
0
0
1
159

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