C8051F540-TB Silicon Laboratories Inc, C8051F540-TB Datasheet - Page 196

• Manufacturer Part Number: C8051F540-TB
• Description: BOARD PROTOTYPE W/C8051F540
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F540-TB

• Contents: Board
• Processor To Be Evaluated: C8051F54x
• Processor Series: C8051F54x
• Interface Type: USB
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F54x
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1672

C8051F54x
196
Bit
MASTER
TXMODE
STA
STO
ACKRQ
ARBLOST
ACK
SI
Set by Hardware When:
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A START is generated.
START is generated.
SMB0DAT is written before the start of an
SMBus frame.
A START followed by an address byte is
received.
A STOP is detected while addressed as a
slave.
Arbitration is lost due to a detected STOP.
A byte has been received and an ACK
response value is needed.
A repeated START is detected as a
MASTER when STA is low (unwanted
repeated START).
SCL is sensed low while attempting to
generate a STOP or repeated START
condition.
SDA is sensed low while transmitting a 1
(excluding ACK bits).
The incoming ACK value is low 
(ACKNOWLEDGE).
A START has been generated.
Lost arbitration.
A byte has been transmitted and an
ACK/NACK received.
A byte has been received.
A START or repeated START followed by a
slave address + R/W has been received.
A STOP has been received.
Table 20.3. Sources for Hardware Changes to SMB0CN
Rev. 1.1
Cleared by Hardware When:
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A STOP is generated.
Arbitration is lost.
A START is detected.
Arbitration is lost.
SMB0DAT is not written before the
start of an SMBus frame.
Must be cleared by software.
A pending STOP is generated.
After each ACK cycle.
Each time SI is cleared.
The incoming ACK value is high
(NOT ACKNOWLEDGE).
Must be cleared by software.