C8051F540-TB Silicon Laboratories Inc, C8051F540-TB Datasheet - Page 165

• Manufacturer Part Number: C8051F540-TB
• Description: BOARD PROTOTYPE W/C8051F540
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F540-TB

• Contents: Board
• Processor To Be Evaluated: C8051F54x
• Processor Series: C8051F54x
• Interface Type: USB
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F54x
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1672

SFR Definition 18.19. P1SKIP: Port 1 Skip
SFR Address = 0xD5; SFR Page = 0x0F
SFR Definition 18.20. P2: Port 2
SFR Address = 0xA0; SFR Page = All Pages; Bit-Addressable
Note: P2.2-P2.7 are only available on the 32-pin packages.
Name
Reset
Name
Reset
Bit
7:0
Bit
7:0
Type
Type
Bit
Bit
P1SKIP[7:0]
P2[7:0]
Name
Name
7
0
7
1
Port 2Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Port 1 Crossbar Skip Enable Bits.
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
6
0
6
1
Description
5
0
5
1
Rev. 1.1
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
4
0
4
1
P1SKIP[7:0]
P2[7:0]
R/W
R/W
Function
Write
3
0
3
1
2
0
2
1
0: P2.n Port pin is logic
LOW.
1: P2.n Port pin is logic
HIGH.
C8051F54x
1
0
1
1
Read
0
0
0
1
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