PIC12HV615-I/SN Microchip Technology, PIC12HV615-I/SN Datasheet - Page 17

• Manufacturer Part Number: PIC12HV615-I/SN
• Description: IC PIC MCU FLASH 1KX14 8SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12HV615-I/SN

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 8-SOIC (3.9mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 5
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC12H
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: RS-232/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162083 - HEADER MPLAB ICD2 PIC16F616 8/14
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
Note
TABLE 2-4:
Addr
 2010 Microchip Technology Inc.
INDF
OPTION_REG
PCL
STATUS
FSR
TRISIO
PCLATH
INTCON
PIE1
PCON
OSCTUNE
PR2
APFCON
WPU
IOC
PMCON1
PMCON2
PMADRL
PMADRH
PMDATL
PMDATH
ADRESL
ANSEL
1:
2:
3:
4:
5:
6:
7:
Name
(2)
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch
exists.
TRISIO3 always reads as ‘1’ since it is an input only pin.
Read only register.
PIC12F615/617/HV615 only.
PIC12F617 only.
—
—
—
—
—
—
—
—
—
(7)
(5, 6)
(7)
(7)
(7)
(7)
(7)
PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Timer2 Module Period Register
Unimplemented
Unimplemented
Program Memory Control Register 2 (not a physical register).
PMADRL7 PMADRL6 PMADRL5 PMADRL4 PMADRL3
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
PMDATL7
GPPU
IRP
Bit 7
GIE
—
—
—
—
—
—
—
—
—
—
—
—
(1)
PMDATL6
INTEDG
ADCS2
RP1
Bit 6
PEIE
ADIE
—
—
—
—
—
—
—
—
—
—
PIC12F609/615/617/12HV609/615
(1)
Program Memory Data Register High Byte.
PMDATL5
TRISIO5
CCP1IE
ADCS1
WPU5
T0CS
IOC5
Bit 5
T0IE
RP0
—
—
—
—
—
—
PMDATL4
TRISIO4
T1GSEL
ADCS0
WPU4
TUN4
T0SE
INTE
IOC4
Bit 4
TO
—
—
—
—
Write Buffer for upper 5 bits of Program Counter
TRISIO3
PMDATL3
CMIE
TUN3
ANS3
GPIE
IOC3
Bit 3
PSA
PD
—
—
—
—
—
(4)
PMADRH2 PMADRH1 PMADRH0 ---- -000
PMADRL2
PMDATL2
TRISIO2
WREN
WPU2
TUN2
ANS2
IOC2
Bit 2
T0IF
PS2
—
—
—
Z
PMADRL1
PMDATL1
TRISIO1
P1BSEL
TMR2IE
WPU1
TUN1
ANS1
IOC1
INTF
POR
Bit 1
PS1
WR
DC
PMADRL0 0000 0000
PMDATL0
TRISIO0
P1ASEL
TMR1IE
GPIF
WPU0
TUN0
ANS0
IOC0
Bit 0
BOR
PS0
RD
C
(3)
xxxx xxxx 25, 116
1111 1111 19, 116
0000 0000 25, 116
0001 1xxx 18, 116
xxxx xxxx 25, 116
--11 1111 44, 116
---0 0000 25, 116
0000 0000 20, 116
-00- 0-00 21, 116
---- --qq 23, 116
---0 0000 41, 116
1111 1111 65, 116
---0 --00 21, 116
--11 -111 46, 116
--00 0000 46, 116
---- -000
---- ----
0000 0000
--00 0000
xxxx xxxx 85, 117
-000 1111 45, 117
DS41302D-page 17
POR, BOR
Value on
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