PIC12HV615-I/SN Microchip Technology, PIC12HV615-I/SN Datasheet - Page 44

• Manufacturer Part Number: PIC12HV615-I/SN
• Description: IC PIC MCU FLASH 1KX14 8SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12HV615-I/SN

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 8-SOIC (3.9mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 5
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC12H
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: RS-232/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162083 - HEADER MPLAB ICD2 PIC16F616 8/14
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12F609/615/617/12HV609/615
REGISTER 5-2:
5.2
Every GPIO pin on the PIC12F609/615/617/12HV609/
615 has an interrupt-on-change option and a weak pull-
up option. The next three sections describe these
functions.
5.2.1
The ANSEL register is used to configure the Input
mode of an I/O pin to analog. Setting the appropriate
ANSEL bit high will cause all digital reads on the pin to
be read as ‘0’ and allow analog functions on the pin to
operate correctly.
The state of the ANSEL bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
5.2.2
Each of the GPIO pins, except GP3, has an individually
configurable internal weak pull-up. Control bits WPUx
enable or disable each pull-up. Refer to Register 5-5.
Each weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset by the GPPU bit of the
OPTION register). A weak pull-up is automatically
enabled for GP3 when configured as MCLR and
disabled when GP3 is an I/O. There is no software
control of the MCLR pull-up.
5.2.3
Each GPIO pin is individually configurable as an
interrupt-on-change pin. Control bits IOCx enable or
disable the interrupt function for each pin. Refer to
Register 5-6. The interrupt-on-change is disabled on a
Power-on Reset.
DS41302D-page 44
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-0
Note 1:
U-0
—
2:
Additional Pin Functions
TRISIO<3> always reads ‘1’.
TRISIO<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
ANSEL REGISTER
WEAK PULL-UPS
INTERRUPT-ON-CHANGE
Unimplemented: Read as ‘0’
TRISIO<5:0>: GPIO Tri-State Control bit
1 = GPIO pin configured as an input (tri-stated)
0 = GPIO pin configured as an output
U-0
—
TRISIO: GPIO TRI-STATE REGISTER
W = Writable bit
‘1’ = Bit is set
TRISIO5
R/W-1
TRISIO4
R/W-1
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TRISIO3
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
GPIO. The ‘mismatch’ outputs of the last read are OR’d
together to set the GPIO Change Interrupt Flag bit
(GPIF) in the INTCON register (Register 2-3).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, clears the
interrupt by:
a)
b)
A mismatch condition will continue to set flag bit GPIF.
Reading GPIO will end the mismatch condition and
allow flag bit GPIF to be cleared. The latch holding the
last read value is not affected by a MCLR nor BOR
Reset. After these resets, the GPIF flag will continue to
be set if a mismatch is present.
R-1
Note:
Any read of GPIO AND Clear flag bit GPIF. This
will end the mismatch condition;
OR
Any write of GPIO AND Clear flag bit GPIF will
end the mismatch condition;
If a change on the I/O pin should occur
when any GPIO operation is being
executed, then the GPIF interrupt flag may
not get set.
TRISIO2
R/W-1
 2010 Microchip Technology Inc.
x = Bit is unknown
TRISIO1
R/W-1
TRISIO0
R/W-1
bit 0