PIC12HV615-I/SN Microchip Technology, PIC12HV615-I/SN Datasheet - Page 24

• Manufacturer Part Number: PIC12HV615-I/SN
• Description: IC PIC MCU FLASH 1KX14 8SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12HV615-I/SN

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 8-SOIC (3.9mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 5
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC12H
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: RS-232/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162083 - HEADER MPLAB ICD2 PIC16F616 8/14
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12F609/615/617/12HV609/615
2.2.2.7
The Alternate Pin Function Control (APFCON) register
is used to steer specific peripheral input and output
functions between different pins. For this device, the
P1A, P1B and Timer1 Gate functions can be moved
between different pins.
The APFCON register bits are shown in Register 2-7.
REGISTER 2-7:
DS41302D-page 24
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3-2
bit 1
bit 0
Note 1: PIC12F615/617/HV615 only.
U-0
—
2: Alternate pin function.
APFCON Register
(PIC12F615/617/HV615 only)
Unimplemented: Read as ‘0’
T1GSEL: TMR1 Input Pin Select bit
1 = T1G function is on GP3/T1G
0 = T1G function is on GP4/AN3/CIN1-/T1G/P1B
Unimplemented: Read as ‘0’
P1BSEL: P1B Output Pin Select bit
1 = P1B function is on GP4/AN3/CIN1-/T1G/P1B
0 = P1B function is on GP0/AN0/CIN+/P1B/ICSPDAT
P1ASEL: P1A Output Pin Select bit
1 = P1A function is on GP5/T1CKI/P1A
0 = P1A function is on GP2/AN2/T0CKI/INT/COUT/CCP1/P1A
U-0
—
APFCON:ALTERNATE PIN FUNCTION REGISTER
W = Writable bit
‘1’ = Bit is set
U-0
—
T1GSEL
R/W-0
(2)
/MCLR/V
(2)
/OSC1/CLKIN
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PP
U-0
—
(2)
(2)
/OSC2/CLKOUT
/OSC2/CLKOUT
U-0
—
(1)
 2010 Microchip Technology Inc.
x = Bit is unknown
P1BSEL
R/W-0
P1ASEL
R/W-0
bit 0