LPC3230FET296/01,5 NXP Semiconductors, LPC3230FET296/01,5 Datasheet - Page 25

• Manufacturer Part Number: LPC3230FET296/01,5
• Description: IC ARM9 MCU 256K 296-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC32x0r

Specifications of LPC3230FET296/01,5

• Package / Case: 296-TFBGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 266MHz
• Connectivity: EBI/EMI, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, Motor Control PWM, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: ROMless
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC32
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 256 KB
• Interface Type: EMC
• Maximum Clock Frequency: 266 MHz
• Number Of Timers: 6
• Operating Supply Voltage: 1.31 V to 1.39 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4964; 935290764551

NXP Semiconductors
LPC3220_30_40_50_1
Preliminary data sheet
7.5.1.1 Multi-Level Cell (MLC) NAND flash controller
7.4.1 On-chip ROM
7.4.2 On-chip SRAM
7.5.1 NAND flash controllers
7.4 Internal memory
7.5 External memory interfaces
The built-in 16 kB ROM contains a program which runs a boot procedure to load code
from one of four external sources, UART5, SSP0 (SPI mode), EMC Static CS0 memory, or
NAND FLASH.
After reset, execution always begins from the internal ROM. The bootstrap software first
reads the SERVICE input (GPI_1). If SERVICE is LOW, the bootstrap starts a service boot
and can download a program over serial link UART5 to IRAM and transfer execution to the
downloaded code.
If the SERVICE pin is HIGH, the bootstrap routine jumps to normal boot. The normal boot
process first tests SPI memory for boot information if present it uploads the boot code and
transfers execution to the uploaded software. If the SPI is not present or no software is
loaded, the bootloader will test the EMC Static CS0 memory for the presence of boot code
and if present boots from static memory, If this test fails the boot loader will test external
NAND flash for boot code and boot if code is present.
The boot loader consumes no user memory space because it is in ROM.
On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed
as 8, 16, or 32 bit memory. The LPC3220/30/40/50 provides 256 kB of internal SRAM.
The LPC3220/30/40/50 includes three external memory interfaces, NAND Flash
controllers, Secure Digital Memory Controller, and an external memory controller for
SDRAM, DDR SDRAM, and Static Memory devices.
The LPC3220/30/40/50 includes two NAND flash controllers, one for multi-level cell NAND
flash devices and one for single-level cell NAND flash devices. The two NAND flash
controllers use the same pins to interface to external NAND flash devices, so only one
interface is active at a time.
The MLC NAND flash controller interfaces to either multi-level or single-level NAND flash
devices. An external NAND flash device is used to allow the bootloader to automatically
load a portion of the application code into internal SRAM for execution following reset.
The MLC NAND flash controller supports small (528 byte) and large (2114 byte) pages.
Programmable NAND timing parameters allow support for a variety of NAND flash
devices. A built-in Reed-Solomon encoder/decoder provides error detection and
correction capability. A 528 byte data buffer reduces the need for CPU supervision during
loading. The MLC NAND flash controller also provides DMA support.
Rev. 01 — 6 February 2009
LPC3220/30/40/50
16/32-bit ARM microcontrollers
© NXP B.V. 2009. All rights reserved.
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