LPC3230FET296/01,5 NXP Semiconductors, LPC3230FET296/01,5 Datasheet - Page 54

IC ARM9 MCU 256K 296-TFBGA

LPC3230FET296/01,5

Manufacturer Part Number
LPC3230FET296/01,5
Description
IC ARM9 MCU 256K 296-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC32x0r
Datasheets

Specifications of LPC3230FET296/01,5

Package / Case
296-TFBGA
Core Processor
ARM9
Core Size
16/32-Bit
Speed
266MHz
Connectivity
EBI/EMI, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, Motor Control PWM, PWM, WDT
Number Of I /o
51
Program Memory Type
ROMless
Ram Size
256K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 3.6 V
Data Converters
A/D 3x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC32
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
256 KB
Interface Type
EMC
Maximum Clock Frequency
266 MHz
Number Of Timers
6
Operating Supply Voltage
1.31 V to 1.39 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 3 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4964
935290764551

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC3230FET296/01,5
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
Table 12.
C
[1]
[2]
[3]
[4]
LPC3220_30_40_50_1
Preliminary data sheet
Symbol Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
oper
CK
CL
CH
d(V)ctrl
h(ctrl)
d(AV)
h(A)
su(Q)
h(Q)
DQSH
DQSL
DQSS
DSS
DSH
d(DQS)
su(D)
h(D)
WPRE
WPST
RPRE
RPST
L
= 25 pF; T
All values valid for EMC pads set to high slew rate at 1.8 V.
CMD_DLY = COMMAND_DELAY bitfield in SDRAMCLK_CTRL[18:14] register, see External memory controller (EMC) chapter in
LPC32x0 User manual .
Applies to signals EMC_DQM[1:0], EMC_DYCSm, EMC_RAS, EMC_CAS, EMC_WR, EMC_CKEm.
DQS_DELAY, see LPC32x0 user manual, External Memory Controller Chapter, Section 8 DDR DQS delay calibration for details on
configuring this value.
operating frequency
clock cycle time
CK LOW-level width
CK HIGH-level width
control valid delay time
control hold time
address valid delay time
address hold time
data output set-up time
data output hold time
DQS HIGH time
DQS LOW time
WRITE command to first DQS latching
transition time
DQS falling edge to CK set-up time
DQS falling edge hold time from CK
DQS delay time
data input set-up time
data input hold time
write preamble time
write postamble time
read preamble time
read postamble time
EMC DDR SDRAM memory interface dynamic characteristics
amb
= 25 C.
Rev. 01 — 6 February 2009
Conditions
EMC_D and
EMC_DQM to
EMC_DQS
out
EMC_D and
EMC_DQM to
EMC_DQS
out
for WRITE
command
for WRITE
command
for DQS out
for DQS in
for DQS in
for DQS in
[2][3]
[2][3]
[2]
[2]
[4]
Min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
[1]
Typical
104
9.6
0.5
0.5
(CMD_DLY
(CMD_DLY
(CMD_DLY
(CMD_DLY
0.275
0.225
0.5
0.5
t
0.5
0.5
DQS_DELAY
0.3
0.5
<tbd>
<tbd>
<tbd>
<tbd>
CK
LPC3220/30/40/50
+ (CMD_DLY
t
t
t
t
t
t
16/32-bit ARM microcontrollers
CK
CK
CK
CK
CK
CK
t
t
CK
CK
0.25) + 1.5
0.25)
0.25) + 1.5
0.25)
0.25)
1.5
1.5
© NXP B.V. 2009. All rights reserved.
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
54 of 73
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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