MC908JB8ADWE Freescale Semiconductor, MC908JB8ADWE Datasheet - Page 102
![IC MCU 3MHZ 8K FLASH 28-SOIC](/photos/12/16/121605/mc908jb8adwe_sml.jpg)
MC908JB8ADWE
Manufacturer Part Number
MC908JB8ADWE
Description
IC MCU 3MHZ 8K FLASH 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908JB8JDWE.pdf
(286 pages)
Specifications of MC908JB8ADWE
Core Processor
HC08
Core Size
8-Bit
Speed
3MHz
Connectivity
USB
Peripherals
LVD, POR, PWM
Number Of I /o
21
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
HC08JB
Core
HC08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
USB
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
5.25 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
Minimum Operating Temperature
0 C
Controller Family/series
HC08
No. Of I/o's
21
Ram Memory Size
256Byte
Cpu Speed
8MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908JB8ADWE
Manufacturer:
FREESCALE
Quantity:
20 000
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System Integration Module (SIM)
8.4.2.5 Low-Voltage Inhibit (LVI) Reset
8.4.2.6 Universal Serial Bus Reset
8.4.2.7 Registers Values After Different Resets
Technical Data
102
NOTE:
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the V
reset status register (RSR) is set, and the external reset pin (RST) is held
low while the SIM counter counts out 4096 OSCXCLK cycles. Sixty-four
OSCXCLK cycles later, the CPU is released from reset to allow the reset
vector sequence to occur. The SIM actively pulls down the RST pin for
all internal reset sources.
The USB module will detect a reset signaled on the bus by the presence
of an extended SE0 at the USB data pins of a device. The MCU seeing
a single-ended 0 on its USB data inputs for more than 2.5
signal as a reset. After the reset is removed, the device will be in the
attached, but not yet addressed or configured, state (refer to Section 9.1
USB Devices of the Universal Serial Bus Specification Rev. 1.1). The
device must be able to accept the device address via a SET_ADDRESS
command (refer to Section 9.4 of the Universal Serial Bus Specification
Rev. 1.1) no later than 10ms after the reset is removed.
USB reset can be disabled to generate an internal reset, instead, a USB
interrupt can be generated. (See
(CONFIG).)
USB reset is disabled when the USB module is disabled by clearing the
USBEN bit of the USB Address Register (UADDR).
Some registers are reset by POR or LVI reset only.
registers or register bits which are unaffected by normal resets.
DD
voltage falls to the LVI reset voltage, V
System Integration Module (SIM)
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Section 5. Configuration Register
TRIP
Freescale Semiconductor
Table 8-3
. The LVI bit in the
µ
s treats that
shows the
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