MC908JB8ADWE Freescale Semiconductor, MC908JB8ADWE Datasheet - Page 97
![IC MCU 3MHZ 8K FLASH 28-SOIC](/photos/12/16/121605/mc908jb8adwe_sml.jpg)
MC908JB8ADWE
Manufacturer Part Number
MC908JB8ADWE
Description
IC MCU 3MHZ 8K FLASH 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908JB8JDWE.pdf
(286 pages)
Specifications of MC908JB8ADWE
Core Processor
HC08
Core Size
8-Bit
Speed
3MHz
Connectivity
USB
Peripherals
LVD, POR, PWM
Number Of I /o
21
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
HC08JB
Core
HC08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
USB
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
5.25 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
Minimum Operating Temperature
0 C
Controller Family/series
HC08
No. Of I/o's
21
Ram Memory Size
256Byte
Cpu Speed
8MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908JB8ADWE
Manufacturer:
FREESCALE
Quantity:
20 000
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8.3.1 Bus Timing
8.3.2 Clock Startup from POR or LVI Reset
8.3.3 Clocks in Stop Mode and Wait Mode
8.4 Reset and System Initialization
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
In user mode, the internal bus frequency is the oscillator frequency
divided by two.
When the power-on reset (POR) module or the low-voltage inhibit
module generates a reset, the clocks to the CPU and peripherals are
inactive and held in an inactive phase until after the 4096 OSCXCLK
cycle POR timeout has completed. The RST pin is driven low by the SIM
during this entire period. The IBUS clocks start upon completion of the
timeout.
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
OSCXCLK to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay timeout. This timeout is
selectable as 4096 or 2048 OSCXCLK cycles. (See
In wait mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
The MCU has these reset sources:
•
•
•
•
•
•
•
Power-on reset module (POR)
External reset pin (RST)
Computer operating properly module (COP)
Illegal opcode
Illegal address
Universal serial bus module (USB)
Low-voltage inhibit module (LVI)
System Integration Module (SIM)
System Integration Module (SIM)
Reset and System Initialization
8.7.2 Stop
Technical Data
Mode.)
97
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