MC908JB8ADWE Freescale Semiconductor, MC908JB8ADWE Datasheet - Page 200

• Manufacturer Part Number: MC908JB8ADWE
• Description: IC MCU 3MHZ 8K FLASH 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JB8ADWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: USB
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Input/Output Ports (I/O)
Technical Data
200
* DDRA7 bit is reset by POR or LVI reset only.
Addr.
$0000
$0001
$0002
$0003
$0004 Data Direction Register A
$0005 Data Direction Register B
$0006 Data Direction Register C
$0007 Data Direction Register D
$0008
Register Name
Port C Data Register
Port D Data Register
Port A Data Register
Port B Data Register
Port E Data Register
NOTE:
(DDRC)
(DDRD)
(DDRA)
(DDRB)
(PTA)
(PTB)
(PTC)
(PTD)
(PTE)
Connect any unused I/O pins to an appropriate logic level, either V
or V
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Figure 12-1. I/O Port Register Summary
SS
. Although the I/O ports do not require termination for proper
DDRA7
DDRB7
DDRC7
DDRD7
PTC7
PTD7
PTA7
PTB7
Bit 7
0*
0
0
0
0
Input/Output Ports (I/O)
= Unimplemented
DDRA6
DDRB6
DDRC6
DDRD6
PTA6
PTB6
PTC6
PTD6
6
0
0
0
0
0
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
DDRA5
DDRB5
DDRC5
DDRD5
PTA5
PTB5
PTC5
PTD5
5
0
0
0
0
0
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
DDRA4
DDRB4
DDRC4
DDRD4
Unaffected by reset
PTA4
PTB4
PTC4
PTD4
PTE4
4
0
0
0
0
DDRA3
DDRB3
DDRC3
DDRD3
PTA3
PTB3
PTC3
PTD3
PTE3
3
0
0
0
0
DDRA2
DDRB2
DDRC2
DDRD2
PTA2
PTB2
PTC2
PTD2
PTE2
Freescale Semiconductor
2
0
0
0
0
DDRC1
DDRD1
DDRA1
DDRB1
PTA1
PTB1
PTC1
PTD1
PTE1
1
0
0
0
0
DDRC0
DDRD0
DDRA0
DDRB0
PTA0
PTB0
PTC0
PTD0
PTE0
Bit 0
REG
0
0
0
0