MC908JB8ADWE Freescale Semiconductor, MC908JB8ADWE Datasheet - Page 239
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MC908JB8ADWE
Manufacturer Part Number
MC908JB8ADWE
Description
IC MCU 3MHZ 8K FLASH 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908JB8JDWE.pdf
(286 pages)
Specifications of MC908JB8ADWE
Core Processor
HC08
Core Size
8-Bit
Speed
3MHz
Connectivity
USB
Peripherals
LVD, POR, PWM
Number Of I /o
21
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
HC08JB
Core
HC08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
USB
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
5.25 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
Minimum Operating Temperature
0 C
Controller Family/series
HC08
No. Of I/o's
21
Ram Memory Size
256Byte
Cpu Speed
8MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908JB8ADWE
Manufacturer:
FREESCALE
Quantity:
20 000
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15.4 I/O Signals
15.4.1 OSCXCLK
15.4.2 STOP Instruction
15.4.3 COPCTL Write
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
NOTE:
NOTE:
Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 OSCXCLK cycles and sets the
COP bit in the reset status register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ is held
at V
the COP.
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
The following paragraphs describe the signals shown in
OSCXCLK is the clock doubler output signal. OSCXCLK frequency is
double of the crystal frequency.
The STOP instruction clears the COP prescaler.
Writing any value to the COP control register (COPCTL) (see
Control
of the SIM counter. Reading the COP control register returns the low
byte of the reset vector.
DD
+ V
Computer Operating Properly (COP)
Register) clears the COP counter and clears bits 12 through 5
HI
. During the break state, V
DD
Computer Operating Properly (COP)
+ V
HI
on the RST pin disables
Figure
Technical Data
15.5 COP
I/O Signals
15-1.
239
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