R5F21256SNFP#U0 Renesas Electronics America, R5F21256SNFP#U0 Datasheet - Page 233

• Manufacturer Part Number: R5F21256SNFP#U0
• Description: IC R8C MCU FLASH 32K 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21256SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Table 14.27
i = 0 or 1
j = either B, C, or D
h = either A, B, C, or D
Count sources
Count operations
PWM waveform
Count start condition
Count stop conditions
Interrupt request generation
timing
TRDIOA0 pin function
TRDIOA1 pin function
TRDIOB0, TRDIOC0, TRDIOD0,
TRDIOB1, TRDIOC1, TRDIOD1
pin functions
INT0 pin function
Read from timer
Write to timer
Select functions
Feb 29, 2008
PWM Mode Specifications
Item
Page 214 of 485
f1, f2, f4, f8, f32, fOCO40M
Increment
Programmable I/O port, pulse output forced cutoff signal input, or INT0
The count value can be read by reading the TRDi register.
External signal input to the TRDCLK pin (valid edge selected by a
program)
PWM period: 1/fk x (m+1)
Active level width: 1/fk x (m-n)
Inactive level width: 1/fk x (n+1)
1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
• 0 (count stops) is written to the TSTARTi bit in the TRDSTR register
• When the CSELi bit in the TRDSTR register is set to 0, the count
• Compare match (The content of the TRDi register matches content of
• TRDi register overflows
Programmable I/O port or TRDCLK (external clock) input
Programmable I/O port
Programmable I/O port or pulse output (selectable by pin)
interrupt input
The value can be written to the TRDi register.
• 1 to 3 PWM output pins selected per 1 channel
• The active level selected by pin.
• Initial output level selected by pin.
• Synchronous operation (Refer to 14.3.3 Synchronous Operation.)
• Buffer operation (Refer to 14.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 14.3.4 Pulse Output
when the CSELi bit in the TRDSTR register is set to 1.
stops at the compare match in the TRDGRAi register.
the TRDGRhi register.)
Forced Cutoff.)
fk: Frequency of count source
m: Value set in the TRDGRAi register
n: Value set in the TRDGRji register
The PWM output pin holds output level before the count stops.
The PWM output pin holds level after output change by compare
match.
Either 1 pin or multiple pins of the TRDIOBi, TRDIOCi or TRDIODi
pin.
n+1
m+1
m-n
Specification
(When “L” is selected as the active level)
14. Timers