MCHC908MR8VFAE Freescale Semiconductor, MCHC908MR8VFAE Datasheet - Page 175
MCHC908MR8VFAE
Manufacturer Part Number
MCHC908MR8VFAE
Description
IC MCU 8K FLASH 8MHZ PWM 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MCHC908MR8VFAE.pdf
(372 pages)
Specifications of MCHC908MR8VFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LVD, POR, PWM
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-LQFP
Processor Series
HC08MR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCHC908MR8VFAE
Manufacturer:
Freescale
Quantity:
8 393
Company:
Part Number:
MCHC908MR8VFAE
Manufacturer:
Freescale Semiconductor
Quantity:
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9.12.4 PWM Control Register 1
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
Reset:
Read:
Write:
PWM control register 1 controls PWM enabling/disabling, the loading of
new modulus, prescaler, and PWM values, and the PWM correction
method. In addition, this register contains the software disable bits to
force the PWM outputs to their inactive states (according to the disable
mapping register).
DISX — Software Disable for Bank X Bit
DISY — Software Disable for Bank Y Bit
PWMINT — PWM Interrupt Enable Bit
dress:
Pulse-Width Modulator for Motor Control (PWMMC)
Ad-
This read/write bit allows the user to disable one or more PWM pins
in bank X. The pins that are disabled are determined by the disable
mapping write-once register.
This read/write bit allows the user to disable one or more PWM pins
in bank Y. The pins that are disabled are determined by the disable
mapping write-once register.
This read/write bit allows the user to enable and disable PWM CPU
interrupts. If set, a CPU interrupt will be pending when the PWMF flag
is set.
1 = Disable PWM pins in bank X
0 = Re-enable PWM pins at beginning of next PWM cycle
1 = Disable PWM pins in Bank Y Bit
0 = Re-enable PWM pins at beginning of next PWM cycle
1 = Enable PWM CPU interrupts
0 = Disable PWM CPU interrupts
DISX
Bit 7
$0020
0
Figure 9-35. PWM Control Register 1 (PCTL1)
= Unimplemented
DISY
6
0
PWMINT
5
0
Pulse-Width Modulator for Motor Control (PWMMC)
PWMF
4
0
3
0
2
0
Control Logic Block
LDOK
1
0
Technical Data
MEN
Bit 0
PW-
0
175
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