MCHC908MR8VFAE Freescale Semiconductor, MCHC908MR8VFAE Datasheet - Page 196
MCHC908MR8VFAE
Manufacturer Part Number
MCHC908MR8VFAE
Description
IC MCU 8K FLASH 8MHZ PWM 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MCHC908MR8VFAE.pdf
(372 pages)
Specifications of MCHC908MR8VFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LVD, POR, PWM
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-LQFP
Processor Series
HC08MR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCHC908MR8VFAE
Manufacturer:
Freescale
Quantity:
8 393
Company:
Part Number:
MCHC908MR8VFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Monitor ROM (MON)
10.5 Security
Technical Data
196
NOTE:
A security feature discourages unauthorized reading of ROM locations
while in monitor mode. The host can satisfy the security feature at
monitor mode entry by sending eight security bytes that match the bytes
at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain
user-defined data.
Do not leave locations $FFF6–$FFFD blank. For security reasons,
program locations $FFF6–$FFFD even if they are not used for vectors.
During monitor mode entry, the MCU waits after the power-on reset for
the host to send the eight security bytes on pin PTB0 (R
received bytes match those at locations $FFF6–$FFFD, the host
satisfies the security feature and can read all ROM locations and
execute code from ROM. Security remains satisfied until a power-on
reset occurs. If the reset was not a power-on reset, security remains
satisfied and security code entry is not required. See
V
RST
PA7
PA0
Notes:
DD
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte.
FROM HOST
FROM MCU
Figure 10-6. Monitor Mode Entry Timing
Monitor ROM (MON)
4096 + 32 CGMXCLK CYCLES
24 BUS CYCLES
1
256 BUS CYCLES (MINIMUM)
4
1
MC68HC908MR8 — Rev 4.1
1
Freescale Semiconductor
Figure
2
X
D). If the
4
10-6.
1
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