MCHC908MR8VFAE Freescale Semiconductor, MCHC908MR8VFAE Datasheet - Page 303
MCHC908MR8VFAE
Manufacturer Part Number
MCHC908MR8VFAE
Description
IC MCU 8K FLASH 8MHZ PWM 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MCHC908MR8VFAE.pdf
(372 pages)
Specifications of MCHC908MR8VFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LVD, POR, PWM
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-LQFP
Processor Series
HC08MR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
MCHC908MR8VFAE
Manufacturer:
Freescale
Quantity:
8 393
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Manufacturer:
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16.9 IRQ Status and Control Register
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
The IRQ status and control register (ISCR) has these functions:
ACK1 — IRQ Interrupt Request Acknowledge Bit
IMASK1 — IRQ Interrupt Mask Bit
MODE1 — IRQ Edge/Level Select Bit
IRQF — IRQ Flag
Reset:
dress:
Read:
Write:
Ad-
•
•
•
Writing a logic 1 to this write-only bit clears the IRQ latch. ACK1
always reads as logic 0. Reset clears ACK1.
Writing a logic 1 to this read/write bit disables IRQ interrupt requests.
Reset clears IMASK1.
This read/write bit controls the triggering sensitivity of the IRQ pin.
Reset clears MODE1.
This read-only bit acts as a status flag, indicating an IRQ event
occurred.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
1 = External IRQ event occurred.
0 = External IRQ event did not occur.
Clears the IRQ interrupt latch
Masks IRQ interrupt requests
Controls triggering sensitivity of the IRQ interrupt pin
Figure 16-4. IRQ Status and Control Register (ISCR)
$003F
Bit 7
R
R
0
0
External Interrupt (IRQ)
= Reserved
R
6
0
0
R
5
0
0
R
4
0
0
IRQF
3
0
IRQ Status and Control Register
ACK1
2
0
0
External Interrupt (IRQ)
IMASK1 MODE1
1
0
Technical Data
Bit 0
0
303
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