MCHC908MR8VFAE Freescale Semiconductor, MCHC908MR8VFAE Datasheet - Page 221
MCHC908MR8VFAE
Manufacturer Part Number
MCHC908MR8VFAE
Description
IC MCU 8K FLASH 8MHZ PWM 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MCHC908MR8VFAE.pdf
(372 pages)
Specifications of MCHC908MR8VFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LVD, POR, PWM
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-LQFP
Processor Series
HC08MR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MCHC908MR8VFAE
Manufacturer:
Freescale
Quantity:
8 393
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Manufacturer:
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MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
NOTE:
NOTE:
Before enabling a TIMA channel register for input capture operation,
make sure that the PTBx/TACHx pin is stable for at least two bus clocks.
TOVx — Toggle-On-Overflow Bit
When TOVx is set, a TIMA counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
PTBx/TCHx
CHxMAX
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIMA counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100 percent. As
Figure 11-8
is set or cleared. The output stays at the 100 percent duty cycle level
until the cycle after CHxMAX is cleared.
TOVx
1 = Channel x pin toggles on TIMA counter overflow.
0 = Channel x pin does not toggle on TIMA counter overflow.
OVERFLOW
Timer Interface A (TIMA)
COMPARE
shows, the CHxMAX bit takes effect in the cycle after it
PERIOD
OUTPUT
Figure 11-8. CHxMAX Latency
OVERFLOW
COMPARE
OUTPUT
OVERFLOW
COMPARE
OUTPUT
OVERFLOW
Timer Interface A (TIMA)
COMPARE
OUTPUT
Technical Data
I/O Registers
OVERFLOW
221
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