MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 136

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 3 Port Integration Module (PIM9NE64V1)
3.4.7
This port is associated with the serial SCI and SPI modules.
Port S pins PS[7:0] can be used either for general-purpose I/O, or with the SCI0, SCI1, and SPI
subsystems.
During reset, port S pins are configured as inputs with pull-up.
3.4.8
This port is associated with the EMAC module.
Port G pins PG[7:0] can be used either for general-purpose I/O or with the EMAC subsystems. Further the
Keypad Wake-Up function is implemented on pins G[7:0].
During reset, port G pins are configured as high-impedance inputs.
3.4.8.1
Port G offers eight general-purpose I/O pins with edge triggered interrupt capability in wired-or fashion.
The interrupt enable as well as the sensitivity to rising or falling edges can be individually configured on
per pin basis. All eight bits/pins share the same interrupt vector. Interrupts can be used with the pins
configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. This external interrupt feature is capable to wake up the CPU when it is in STOP
or WAIT mode.
A digital filter on each pin prevents pulses
interrupt. The minimum time varies over process conditions, temperature and voltage
Table
136
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
3-4).
Port S
Port G
Interrupts
Figure 3-47. Interrupt Glitch Filter on Port G, H, and J (PPS=0)
t
pign
t
pval
MC9S12NE64 Data Sheet, Rev. 1.1
(Figure
3-48) shorter than a specified time from generating an
Freescale Semiconductor
(Figure 3-47
and