MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 225

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

7.3.2.13
The A/D conversion results are stored in 8 read-only result registers. The result data is formatted in the
result registers based on two criteria. First there is left and right justification; this selection is made using
the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using
the DSGN control bit in ATDCTL5. Signed data is stored in 2’s complement format and only exists in left
justified format. Signed data selected for right justified format is ignored.
Read: Anytime
Write: Anytime in special mode, unimplemented in normal modes
7.3.2.13.1
7.3.2.13.2
Freescale Semiconductor
Reset
Reset
Reset
Reset
W
W
W
W
R
R
R
R
R
R
R
R
BIT 9 MSB
BIT 7 MSB
BIT 7 MSB
BIT 1
BIT 7
U
0
0
0
0
0
0
7
7
7
7
Figure 7-17. Right Justified, ATD Conversion Result Register, High Byte (ATDDRxH)
Figure 7-18. Right Justified, ATD Conversion Result Register, Low Byte (ATDDRxL)
Figure 7-15. Left Justified, ATD Conversion Result Register, High Byte (ATDDRxH)
Figure 7-16. Left Justified, ATD Conversion Result Register, Low Byte (ATDDRxL)
ATD Conversion Result Registers (ATDDRx)
Left Justified Result Data
Right Justified Result Data
= Unimplemented or Reserved
= Unimplemented or Reserved
= Unimplemented or Reserved
= Unimplemented or Reserved
BIT 8
BIT 6
BIT 0
BIT 6
BIT 6
U
0
0
0
0
0
0
6
6
6
6
BIT 7
BIT 5
BIT 5
BIT 5
0
0
0
0
0
0
0
0
5
5
5
5
MC9S12NE64 Data Sheet, Rev. 1.1
BIT 6
BIT 4
BIT 4
BIT 4
0
0
0
0
0
0
0
0
4
4
4
4
BIT 5
BIT 3
BIT 3
BIT 3
0
0
0
0
0
0
0
0
3
3
3
3
BIT 4
BIT 2
BIT 2
BIT 2
0
0
0
0
0
0
0
0
2
2
2
2
BIT 9 MSB
Memory Map and Register Definition
BIT 3
BIT 1
BIT 1
BIT 1
0
0
0
0
0
0
0
1
1
1
1
BIT 2
BIT 0
BIT 8
BIT 0
BIT 0
0
0
0
0
0
0
0
0
0
0
0
10-bit data
10-bit data
10-bit data
8-bit data
8-bit data
8-bit data
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