MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 443

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 17
Background Debug Module (BDMV4)
17.1
This section describes the functionality of the background debug module (BDM) sub-block of the HCS12
core platform.
A block diagram of the BDM is shown in
The background debug module (BDM) sub-block is a single-wire, background debug system implemented
in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD
pin.
BDMV4 has enhanced capability for maintaining synchronization between the target and host while
allowing more flexibility in clock rates. This includes a sync signal to show the clock rate and a handshake
signal to indicate when an operation is complete. The system is backwards compatible with older external
interfaces.
17.1.1
Freescale Semiconductor
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Single-wire communication with host development system
BDMV4 (and BDM2): Enhanced capability for allowing more flexibility in clock rates
BDMV4: SYNC command to determine communication rate
BDMV4: GO_UNTIL command
BDMV4: Hardware handshake protocol to increase the performance of the serial communication
Active out of reset in special single-chip mode
Nine hardware commands using free cycles, if available, for minimal CPU intervention
Hardware commands not requiring active BDM
15 firmware commands execute from the standard BDM firmware lookup table
Introduction
Features
SYSTEM
HOST
BDMACT
ENBDM
ENTAG
TRACE
SDV
BKGD
16-BIT SHIFT REGISTER
INSTRUCTION DECODE
Figure 17-1. BDM Block Diagram
MC9S12NE64 Data Sheet, Rev. 1.1
AND EXECUTION
STANDARD BDM
LOOKUP TABLE
FIRMWARE
Figure
17-1.
CONTROL LOGIC
BUS INTERFACE
CLKSW
AND
ADDRESS
DATA
CLOCKS
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