MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 507

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

The total power dissipation can be calculated from:
Two cases with internal voltage regulator enabled and disabled must be considered:
Freescale Semiconductor
Θ
P
INT
JA
1. Internal Voltage Regulator disabled
2. Internal voltage regulator enabled
=
P
Which is the sum of all output currents on I/O ports associated with V
For R
respectively
I
which additionally contains the current flowing into the external loads with output high.
Which is the sum of all output currents on I/O ports associated with V
=
INT
DDX
Package Thermal Resistance, [°C/W]
Chip Internal Power Dissipation, [W]
P
INT
=
DSON
is the current shown in Table A-7 and not the overall current flowing into V
I
DD
=
⋅
I
DDR
is valid:
V
DD
R DSON
+
⋅
V
I
DDPLL
DDR
R DSON
+
=
I
⋅
DDA
V
V DD3 5 ( ) V OH
------------------------------------------- - for outputs driven high
MC9S12NE64 Data Sheet, Rev. 1.1
P IO
DDPLL
P IO
⋅
=
V
P
DDA
=
D
I OH
V OL
----------- - for outputs driven low
I OL
=
+
∑
=
I
i
∑
DDA
–
+
P
i
;
R DSON
I
DDX
INT
R DSON
⋅
V
DDA
;
⋅
+
V
P
DDX
IO
⋅
+
I IO
⋅
I
I IO
DDPHY
+
i
I
2
DDTX
i
2
Power Dissipation and Thermal Characteristics
⋅
V
⋅
V
DDPHY
DDTX
+
DDX
DDX
I
DDTX
.
.
⋅
V
DDTX
DDX
,
507