MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 345

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

MII_COL, MII_CRS, MII_MDC, and MII_MDIO signals are disabled. During loopback, the MII to
external and internal PHYs are disabled. Loopback mode requires that the user set the FDX bit to configure
for full-duplex mode. Loopback connects the outs to the ins and relies on the unidirectional nature of full
duplex to transfer data in parallel. The bidirectional nature of half duplex does not allow the RX to accept
transmit data without using some kind of intermediate storage buffer.
11.4.8
The EMAC provides a software reset capability. When the MACRST bit is set, all registers are reset to
their default values. The EMACE bit is cleared. The receiver and transmitter are initialized. Any reception
and/or transmission currently in progress is abruptly aborted.
11.4.9
When an interrupt event occurs, a bit is set in the IEVENT register. Note that bits in the IEVENT register
are set by the event and remain set until cleared by software. If a bit in the IEVENT register is set and the
corresponding bit is set in the IMASK register, the corresponding interrupt signal asserts. Individual
interrupts are cleared by software by writing a 1 to the corresponding bit in the IEVENT register.
The interrupt sources are listed in
11.4.10 Debug and Stop
During system debug (freeze) mode, the EMAC functions normally.When the system enters low-power
stop mode, the EMAC is immediately disabled. Any receive in progress is dropped and any PAUSE
timeout is cleared. The user must not enter low-power stop mode while TXACT or BUSY is set.
Freescale Semiconductor
Software Reset
Interrupts
Receive Flow Control (RFCIF)
Babbling Receive Error (BREIF)
Receive Error (RXEIF)
Receive Buffer A Overrun (RXAOIF)
Receive Buffer B Overrun (RXBOIF)
Receive Buffer A Complete (RXACIF)
Receive Buffer B Complete (RXBCIF)
MII Management Transfer Complete (MMCIF)
Late Collision (LCIF)
Excessive Collision (ECIF)
Frame Transmission Complete (TXCIF)
Interrupt Source
Table
MC9S12NE64 Data Sheet, Rev. 1.1
Table 11-12. Interrupt Vectors
11-12.
CCR Mask
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
IMASK (RXAOIE)
IMASK (RXBOIE)
IMASK (RXACIE)
IMASK (RXBCIE)
IMASK (BREIE)
IMASK (RXEIE)
IMASK (MMCIE)
IMASK (TXCIE)
IMASK (RFCIE)
IMASK (ECIE)
IMASK (LCIE)
Local Enable
Functional Description
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