HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 139
![IC H8/SLP MCU FLASH 80QFP](/photos/12/20/122049/hd64f38024dv_sml.jpg)
HD64F38024DV
Manufacturer Part Number
HD64F38024DV
Description
IC H8/SLP MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheets
1.US38024-BAG1.pdf
(684 pages)
2.DF36012GFYV.pdf
(1021 pages)
3.DF38102HV.pdf
(145 pages)
Specifications of HD64F38024DV
Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
LCD, PWM, WDT
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F38024DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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4.2.5
Table 4.11 Section Category Options
STARt
Link/Library <Section>[Show entries for :][Section]
Item
Section
address
Symbol
address
file
Command Line Format
STARt = <suboption> [,…]
<suboption>: <section name> [{ : | , } <section name> [,…] ] [ / <address>]
Description
Specifies the start address of the section. Specify an address in the hexadecimal notation.
Two or more sections can be allocated to the same address by separating them with a colon (:).
The section name can be specified using wildcards (*). Sections specified using wildcards are
expanded according to the input order.
Sections specified at a single address are allocated in the specification order.
Objects in a single section are allocated in the specification order of the input file or the input
library.
If no address is specified, the section is allocated at 0.
A section which is not specified with the start option is allocated after the last allocation
address.
Example
start=P,C,D*/100,R1:R2/8000
ROM=D1=R1,D2=R2
Allocates P, C, D1, and D2 to the addresses starting from 0x100 in that order. Both R1 and R2
are allocated to 0x8000.
input=a.obj b.obj
library=c.lib,d.lib;
start=P/100
Remarks
Section Options
Command Line Format
STARt = <sub>[,…]
<sub>: <section name>
FSymbol = <section name>[,…] Link/Library
[{ : | , }<section name>[,…]]
[/<address>]
;
;
a.obj uses symbols in d.lib and b.obj uses symbols in c.lib.
The allocation order in the P section is a(P), b(P), c(P), d(P).
Dialog Menu
Link/Library
<Section>
[Show entries for :]
<Section>
[Show entries for :]
[Section]
[Symbol file]
;
;
D1 and D2 are assumed to be in the section starting
as D.
Specification
Specifies a section start address
Outputs externally defined symbol
addresses to a definition file.
Section Address
125
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