HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 34
HD64F38024DV
Manufacturer Part Number
HD64F38024DV
Description
IC H8/SLP MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheets
1.US38024-BAG1.pdf
(684 pages)
2.DF36012GFYV.pdf
(1021 pages)
3.DF38102HV.pdf
(145 pages)
Specifications of HD64F38024DV
Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
LCD, PWM, WDT
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Quantity
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Company:
Part Number:
HD64F38024DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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noalign specified
<Section B>
align specified (default setting)
<Section B>
align=4 specified
<Section B$4>
<Section B>
<Section B$1>
Size: 8 bytes
Boundary alignment: 2
Size: 10 bytes
Boundary alignment: 2
Example
Size: 4 bytes
Boundary alignment: 4
Size: 2 bytes
Boundary alignment: 2
Size: 2 bytes
Boundary alignment: 1
b
c
d
d
b
d
d
a
a
d
d
a
b
2 bytes
2 bytes
2 bytes
Empty area
Empty area
b
b
d
d
d
d
c
d
b
d
c
<Section B_v>
Size: 6 bytes
Boundary alignment: 2
<Section B_v$4>
<Section B_v>
Size: 4 bytes
Boundary alignment: 4
Size: 6 bytes
Boundary alignment: 2
<Section B_v>
Size: 2 bytes
Boundary alignment: 2
e
e
e
f
f
f
f
f
f
e
e
f
f
e
f
f
f
f
o Data are categorized into the following 3 groups:
o The original data section is divided into the above
X: The section consting of data whose size is a multiple of 4
Y: The section consisting of data whose size is odd
Z: The other data remains in the original section
o 2-byte aligned data is allocated before
o Data is located in the order of declaration.
o 2-byte-aligned data is always located
Y. data whose size is odd
X. data whose size is a multiple of 4
Z. the others (data whose size is even but is not
3 groups. For example, the B section will be
divided into B$4, B$1 and B as shown below.
is aligned on a 4-byte boundary and "$4" is appended
after the original section name. (e.g. B$4)
is aligned on a 1-byte boundary and "$1" is appended
after the original section name. (e.g. B$1)
whose boundary alignment is 2-byte and
the section name is unchanged. (e.g. B)
1-byte aligned data in order to
minimize the empty area.
at an even address, thus generating
an empty area being unused
after odd-size data.
a multiple of 4)
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