HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 88
HD64F38024DV
Manufacturer Part Number
HD64F38024DV
Description
IC H8/SLP MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheets
1.US38024-BAG1.pdf
(684 pages)
2.DF36012GFYV.pdf
(1021 pages)
3.DF38102HV.pdf
(145 pages)
Specifications of HD64F38024DV
Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
LCD, PWM, WDT
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
HD64F38024DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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OPtimize, NOOPtimize
Assembly <Object> [Optimize]
Note:
Note: Only valid when an absolute symbol that is defined after the instruction is referenced.
74
The frist operand
@(disp,Reg)
@(disp,@ERn.sz)
@(disp,@+ERn.sz) or @(disp,@-ERn.sz)
@(disp,@ERn+.sz) or @(disp,@ERn-.sz)
@(disp,@(disp,Reg).sz)
@(disp,@abs.sz)
Type of Displacement
Absolute value (-32768 to 32767)
Relative value
External reference value
Command Line Format
OPtimize
NOOPtimize
Description
The optimize option specifies whether or not to optimize the PC relative format, displacement
size of register-indirect with displacement, and address size of the absolute addressing format.
Regarding the MOVA instruction of H8SX, the optimization is performed or not as shown in
the table below.
This option is valid for executable instructions when a displacement (:8 or :16) is not specified,
or an allocated size (:8, :16, :24, or :32) of an absolute address is not specified. The
displacement size is set as shown below according to the displacement value of the PC relative
format.
When no optimization is specified in the H8S/2600 advanced mode:
1. “Reg” can be RnL.B, RnH.B, Rn.W or En.W.
2. “sz” can be either B or W.
3. “Reg” can be ERn, RnL.B, Rn.W or ERn.L.
*1
*2
*2
*2 *3
Size
16 bits*
16 bits
16 bits
*2
*2
Whether optimized or not
Yes
Yes
Yes
Yes
No
No
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