HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 55

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.2.5
Table 2.8
Item
Comment
nesting
Embedded
C++ language
MAC register
Disable of loop
iteration
condition
optimization
Enumeration
data size
Increase of
registers for
register
variables
Common
subexpression
elimination
Other Options
Other Options
Command Line
Format
COMment
ECpp
MAcsave
VOLATILE_Loop
Byteenum
Regexpansion
NORegexpansion
CMncode
Dialog Menu
C/C++ <Other>
[Miscellaneous options :]
C/C++ <Other>
[Miscellaneous options :]
C/C++ <Other>
[Miscellaneous options :]
C/C++ <Other>
[Miscellaneous options :]
qualified]
C/C++ <Other>
[Miscellaneous options :]
C/C++ <Other>
[Miscellaneous options :]
C/C++ <Other>
[Miscellaneous options :]
[Allow comment nest]
[Check against EC++ language
[Interrupt handler saves/restores
[Treats loop condition as volatile
[Treat enum as char if it is in the
[Increase a register for register
[Put common subexpression on a
specification]
MACH and MACL registers if used]
range of char]
variable]
register temporarily]
Specification
Allows comment (/* */)
nesting.
Checks the syntax
according to the EC++
language specifications
and determines the used
memory management
libraries.
Always keeps the MAC
register contents
unchanged after an
interrupt function is
called.
Disables optimization of
loop iteration condition.
Handles enumeration
data declared by enum
with char.
Uses (E)R3 to (E)R6
Uses (E)R4 to (E)R6
Optimizes with common
subexpression
elimination.
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