M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 327
M30853FJGP#U3
Manufacturer Part Number
M30853FJGP#U3
Description
IC M32C MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30853FHFPD5.pdf
(94 pages)
3.M30853FHFPU3.pdf
(544 pages)
Specifications of M30853FJGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30853FJGP#U3M30853FJGP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Table 5.1.1 Interrupt Source (Nonmaskable) and Fixed Vector Table
Table 5.1.2 Interrupt Exclusively for Emulator (Nonmaskable) and Vector Table
_______
Undefined instruction
Overflow
BRK instruction
Address match
Watchdog timer
NMI
Reset
BRK2 instruction
Single step
e
E
v
Interrupt source
J
Chapter 5
1 .
0
Interrupt source
9
0 .
B
0
0
3
1
2
Maskable interrupt:
Nonmaskable interrupt: This type of interrupt cannot be controlled by using the I flag to enable (or
9
0
0 -
0
6
1
0 .
0
0
5
3 .
Interrupt
1
p
a
g
e
FFFFDC
Address (L) to address (H)
FFFFE8
FFFFFC
FFFFE4
FFFFF8
FFFFE0
FFFFF0
Vector table addresses
Interrupt vector table register exclusively for
emulator
000020
309
f o
16
16
16
16
16
16
16
16
3
This type of interrupt can be controlled by using the I flag to enable (or
disable) an interrupt or by changing the interrupt priority level.
disable) an interrupt or by changing the interrupt priority level.
3
to 000023
to FFFFEB
to FFFFFB
to FFFFE7
to FFFFF3
to FFFFE3
to FFFFFF
to FFFFDF
5
Address (L) to address (H)
Vector table addresses
16
16
16
16
16
16
16
16
Interrupt generated by the UND instruction.
Interrupt generated by the INTO instruction.
Executed beginning from address indicated by
vector in variable vector table if content of address
FFFFE7
Can be controlled by an interrupt enable bit.
External interrupt generated by driving NMI pin low.
16
is FF
16
.
Remarks
This interrupt is used
exclusively for debugger
purposes.
Remarks
5.1 Outline of Interrupt
_______
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