M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 333

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Chapter 5
Figure 5.3.1. Interrupt response time
1 .
0
5.3.1 Interrupt Response Time
9
0 .
B
(a) Time from when interrupt request is generated to when the instruction then under execu-
(b) Time in which the interrupt sequence is executed
The interrupt response time means a period of time from when an interrupt request is generated till when
the first instruction of the interrupt routine is executed. This period consists of time (a) from when an
interrupt request is generated to when the instruction then under way is completed and time (b) in which
an interrupt sequence is executed. Figure 5.3.1 shows the interrupt response time.
Time (a) varies with each instruction being executed. The DIVX instruction requires a maximum time that
consists of 29* cycles.
Time (b) is shown in table 5.3.1.
addressing modes are modified by the INDEX instructions, add 1 cycle.
0
0
Interrupt request generated
3
1
2
tion is completed
9
0
0 -
0
* It is when the divider is immediate or register. When the divider is memory, the following value is
6
1
When X and Y are in odd address or in 8 bits bus area, double the value of X and Y. When above
0 .
added.
X is number of wait of the divider area. Y is number of wait of the indirect address stored area.
0
0
5
3 .
Interrupt
1
• General instruction addressing
• Indirect instruction addressing
p
a
g
e
315
Instruction
f o
Interrupt response time
3
(a)
3
Interrupt request acknowledged
5
Interrupt sequence
(b)
: 2 + X
: 5 + X + 2Y
Instruction in interrupt
routine
5.3 Interrupt Sequence
Time