M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 342

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
e
E
v
J
Chapter 6
Figure 6.1.2. When executing a register transfer instruction starting from an odd address
1 .
0
9
0 .
B
Content at jump address is
prefetched at the same time the
instruction queue buffer is cleared.
Fetch code
Instruction
queue buffer
Address bus
Instructions
under execution
BCLK
Data bus (H)
Data bus (L)
0
0
3
1
2
9
0
Sample program
Address
FFC024
FFC024
FFC025
FFC026
FFC027
FFC028
FFC029
FFC02A
FFC02B
FFC02C
FFC02D
FFC02D
FFC02F
FFC030
FFC031
FFC032
FFC033
FFC034
FFC035
FFC036
FFC037
0 -
0
6
1
WR
RD
0 .
0
0
5
3 .
(Program area: 16-bit bus without wait state; Data area: 16-bit bus without wait state)
Calculation number of cycles
1
p
Code
a
Jump address
7B
DE
DE
DE
DE
DE
DE
DE
DE
C9EB
7A
DE
DE
DE
DE
DE
DE
DE
g
TEST_10:
e
TEST_11:
TEST_12:
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
: Indicates the locations of the instruction queue buffer that are cleared.
324
FFC02A FFC02D FFC02E FFC030 FFC032 FFC034 FFC037 FFC038 FFC03A
7B
DE
DE
DE
DE
DE
DE
DE
f o
Instruction
DE
DE
P
JMP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MOV.W:G
JMP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
3
3
JMP TEST_11
5
C9
P
C9
C9
EB
7A
TEST_11
R0,R1
TEST_12
Fetch
EB
P
7A
DE
DE
C9
EB
7A
DE
DE
P
MOV.W
C9EB
DE
DE
DE
DE
7A
DE
DE
P
Fetch
DE
DE
DE
DE
DE
DE
7A
DE
DE
P
JMP TEST_12
C9
P
C9
Not all codes are ready in the
instruction queue buffer, so
the next read is performed
6.1 Instruction queue buffer
EB
BB
C9
BB
EB
P
EB
BB
C9
FF
9E
P
9E
FF