M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 330

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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5.2 Interrupt Control
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Chapter 5
The following explains how to enable/disable maskable interrupts and set acknowledge priority. The expla-
nation here does not apply to nonmaskable interrupts.
Maskable interrupts are enabled and disabled by using the interrupt enable flag (I flag), interrupt priority
level select bit, and processor interrupt priority level (IPL). Whether there is any interrupt requested is
indicated by the interrupt request bit. The interrupt request bit and interrupt priority level select bit are
arranged in the interrupt control register provided for each specific interrupt. The interrupt enable flag (I
flag) and processor interrupt priority level (IPL) are arranged in the flag register (FLG).
For details about the memory allocation and the configuration of interrupt control registers, refer to the
M32C User's Manual.
Figure 5.2.1 Timing at which changes of I flag are reflected in interrupt handling
1 .
0
5.2.1 Interrupt Enable Flag (I Flag)
5.2.2 Interrupt Request Bit
9
When changed by REIT or FREIT instruction
When changed by FCLR, FSET, POPC, or LDC instruction
0 .
B
The interrupt enable flag (I flag) is used to disable/enable maskable interrupts. When this flag is set (=
1), all maskable interrupts are enabled; when the flag is cleared to 0, they are disabled. This flag is
automatically cleared to 0 after a reset.
When the I flag is changed, the altered flag status is reflected in determining whether or not to accept an
interrupt request at the following timing:
This bit is set (= 1) when an interrupt request is generated. This bit remains set until the interrupt request
is acknowledged. The bit is cleared to 0 when the interrupt request is acknowledged.
This bit can be cleared to 0 (but cannot be set to 1) in software.
0
0
3
1
2
9
0
0 -
0
• If the flag is changed by an REIT or FREIT instruction, the changed status takes effect begin-
• If the flag is changed by an FCLR, FSET, POPC, or LDC instruction, the changed status takes
6
1
0 .
ning with that REIT or FREIT instruction.
effect beginning with the next instruction.
0
0
5
3 .
Interrupt request generated
Interrupt
Interrupt request generated
1
p
a
g
e
Previous
instruction
(If I flag is changed from 0 to 1 by REIT instruction)
Previous
instruction
312
(If I flag is changed from 0 to 1 by FSET instruction)
f o
3
3
5
Determination whether or not to
accept interrupt request
FSET I
REIT
Interrupt sequence
Next instruction
Determination whether or not to
accept interrupt request
Interrupt sequence
Time
Time
5.2 Interrupt Control