M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 345

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
e
E
v
J
Chapter 6
Figure 6.1.5. When executing an instruction to transfer data between even addresses starting from an even address
1 .
0
9
0 .
B
0
Data bus (H)
Data bus (L)
0
Address bus
Instructions
under execution
Fetch code
Instruction
queue buffer
BCLK
WR
RD
3
1
2
Content at jump
address is prefetched at
the same time the
instruction queue buffer
is cleared.
9
0
0 -
0
6
1
0 .
0
0
5
3 .
(Program area: 16-bit bus without wait state; Data area: 16-bit bus without wait state)
Calculation number of cycles
DW : Indicates a data write.
DR : Indicates a data read.
1
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
Jump address
Sample program
Address
FFC024
FFC024
FFC025
FFC026
FFC027
FFC028
FFC029
FFC02A
FFC02B
FFC02C
FFC02C
FFC032
FFC033
FFC034
FFC035
FFC036
FFC037
FFC038
FFC039
FFC03A
p
: Indicates the locations of the instruction queue buffer that are cleared.
FFC02A FFC02C FFC02E FFC030
a
g
7A
DE
DE
DE
DE
DE
DE
DE
e
JMP TEST_11
DE
DE
P
327
B7
FB
f o
Code
P
FB
B7
7A
DE
DE
DE
DE
DE
DE
DE
B7FB00200220
7A
DE
DE
DE
DE
DE
DE
DE
TEST_10:
TEST_11:
TEST_12:
3
3
5
B7
FB
00
20
P
20
00
Fetch
B9FB
00
20
02
20
20
02
P
Instruction
Fetch
02000
JMP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MOV.W
JMP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
0020
02
20
DR
MOV.W
AA
AA
FFC032
DE
7A
Content at address 2000
02
20
Content at address 2001
TEST_11
02000h,02002h
TEST_12
P
DE
7A
FFC034 02002
DE
DE
DE
02
20
7A
P
DE
DE
02207A
Fetch
DE
DE
DE
DW
JMP TEST_12
P
AA
AA
FFC03A FFC03C
16
16
FB
B7
6.1 Instruction queue buffer
P
FB
B7
Content at jump address
is prefetched at the
same time the instruction
queue buffer is cleared.
B7
FB
00
20
P
20
00