M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 66

IC M32C MCU FLASH 100LQFP

M30853FJGP#U3

Manufacturer Part Number
M30853FJGP#U3
Description
IC M32C MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30853FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R
R
e
E
v
ADDX
[ Syntax ]
[ Operation ]
[ Function ]
[ Flag Change ]
[ Description Example ]
J
[ Selectable src/dest ]*
Chapter 3
1 .
*1 Indirect instruction addressing [src] and [dest] can be used in all addressing except R0L/R0/R2R0, R0H/
Change
0
Conditions
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
#IMM8
9
ADDX
dest
dest
Flag
0 .
B
• Sign-extend the 8-bit
• When
O :
S :
Z :
C :
ADDX
ADDX
ADDX
R2/-, R1L/R1/R3R1, R1H/R3/-, and #IMM.
0
0
operation. The 24 low-order bits of the operation result are stored in
states depending on the result of 32-bit operation. Also, when
extended to be treated as 8 low-order-bit data for the operation.
3
1
2
9
0
0 -
U
0
The flag is set when a signed operation resulted in exceeding +2147483647(.L) or
-2147483648(.L); otherwise cleared.
The flag is set when the operation resulted in MSB = 1; otherwise cleared.
The flag is set when the operation resulted in 0; otherwise cleared.
The flag is set when an unsigned operation resulted in exceeding +4294967295(.L); otherwise
cleared.
6
1
0 .
0
dest
0
dest
dest
5
I
3 .
A1/A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
Functions
1
src,dest
R0L,A0
RAM:8[SB],R2R0
[A0],A1
is the address register (A0, A1) ,
O
p
+
+
a
g
e
B
EXTS(src)
EXTS([src])
1
src
48
src
S
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB] dsp:16[FB]
abs24
f o
to 32 bits which are added to the 32-bit
Z
3
3
5
D
Add extend sign without carry
ADDition eXtend sign
C
abs16
[A1]
dsp:8[FB]
[dest]
[dest]
dest
[dest]
[dest]
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
is zero-extended to be treated as 32-bit data for the
+
+
EXTS(src)
EXTS([src])
[ Instruction Code/Number of Cycles ]
dsp:24[A1]
A1/A1/A1
dsp:8[A1]
dsp:16[A1]
src
dest
is the address register,
, and the result is stored in
dest
dest
R0H/R2/-
R1H/R3/-
[A0]
abs24
dsp:8[SB]
dsp:16[SB] dsp:16[FB]
. The flags also change
3.2
ADDX
[A1]
dsp:8[FB]
abs16
src
Page=
Functions
is zero-
dest
183
.

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