M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 54
M30853FJGP#U3
Manufacturer Part Number
M30853FJGP#U3
Description
IC M32C MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30853FHFPD5.pdf
(94 pages)
3.M30853FHFPU3.pdf
(544 pages)
Specifications of M30853FJGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30853FJGP#U3M30853FJGP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R
e
E
v
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Chapter 2 Addressing Modes
1 .
0
When (.W) is specified for the size specifier (.size)
• Read
• Write
When (.L) is specified for the size specifier (.size)
• Read
• Write
9
The low order 16-bit are read. The flags change
states depending on the result of 16-bit operation.
Write to the low order 16-bit. In this case, the 8
high-order bits become 0. The flags change states
depending on the result of 16-bit transfer data.
32 bits are read out after being zero-extended.
The flag varies depending on the result of a 32-bit
operation.
The low-order 24-bit is written, with the 8 high-
order bit ignored. The flag varies depending on
the result of a 32-bit operation (not the value of the
24-bit register).
The value of A0 after executing the above instruc-
tion becomes 000000
is performed on 32-bit data, the S flag is set to 1
and the Z flag is cleared to 0.
0 .
B
0
0
3
1
Example:
2
9
0
0 -
0
6
1
0 .
0
0
5
3 .
1
p
MOV.L#80000000h,A0
Flag status after execution
S flag = 1 (The MSB is bit 31.)
Z flag = 0 (Set to 1 when all of 32
a
g
e
16
36
. However, since operation
f o
bits are 0s.)
3
3
5
2.7 Read and write operations with 24-bit registers
A0/A1
A0/A1
A0/A1
Zero-expanded
A0/A1
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
b31
b31
b31
00
00
16
16
b23
b24
b23
b24
b24
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
b23
b23
b23
b23
b16
b16
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
b15
b15
b16
b16
b16
b16
b15
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
b15
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
b15
b15
b15
b15
b8
b8
Read
Write
b8
b8
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
b7
b7
b7
b8
b8
b7
b8
b8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
b7
b7
b7
b7
b0
b0
Read
b0
b0
Write
b0
b0
b0
b0
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