M30833FJGP#U3 Renesas Electronics America, M30833FJGP#U3 Datasheet - Page 132

• Manufacturer Part Number: M30833FJGP#U3
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 87
• Interface Type: UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
10.10 Address Match Interrupt
3
. v
J
Figure 10.12 AIER Register and RMAD0 to RMAD3 Registers
2
0
1
The address match interrupt occurs immediately before executing an instruction that is stored into an ad-
dress indicated by the RMADi register (i=0 to 3). The address match interrupt can be set in four addresses.
The AIERi bit in the AIER register determines whether the interrupt is enabled or disabled. The I flag and
IPL do not affect the address match interrupt.
Figure 10.12 shows registers associated with the address match interrupt.
Set the starting address of an instruction in the RMADi register. The address match interrupt does not
occur when a table data or addresses other than the starting address of the instruction is set.
C
9
3 .
B
8 /
0
1
3
0
Address Match Interrupt Enable Register
3
b7
J
G
4
a
Address Match Interrupt Register i
b23
0 -
n
o r
b6
3 .
1
u
, 1
3
p
b5
1
b16 b15
2
(
M
0
b4
0
3
6
2
b3
C
8 /
Page 107
b8 b7
b2
, 3
b1
M
3
b0
2
b0
C
f o
(b7 - b4)
8 /
Addressing Register for the Address Match Interrupt
AIER0
AIER1
AIER2
AIER3
Symbol
4
3
Bit
8
) T
Symbol
AIER
8
Symbol
RMAD0
RMAD1
RMAD2
RMAD3
Address Match
Interrupt 0 Enable Bit
Address Match
Interrupt 1 Enable Bit
Address Match
Interrupt 2 Enable Bit
Address Match
Interrupt 3 Enable Bit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Bit Name
Function
Address
0012
0016
001A
001E
0009
Address
16
16
16
16
16
- 0010
- 0014
- 0018
- 001C
16
16
16
16
0 : Disables the interrupt
1 : Enables the interrupt
0 : Disables the interrupt
1 : Enables the interrupt
0 : Disables the interrupt
1 : Enables the interrupt
0 : Disables the interrupt
1 : Enables the interrupt
After Reset
000000
000000
000000
000000
000000
After Reset
XXXX 0000
Setting Range
Function
16
16
16
16
16
to FFFFFF
2
16
RW
RW
RW
RW
RW
RW
RW
10. Interrupts