M30833FJGP#U3 Renesas Electronics America, M30833FJGP#U3 Datasheet - Page 504

• Manufacturer Part Number: M30833FJGP#U3
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 87
• Interface Type: UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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27.12 Intelligent I/O
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27.12.1 Register Setting
27.12.2 BTSR Register Setting
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Operations controlled by the values written to the GiBT (i=0 to 3), GiBCR1, BTSR, GjTMCR0 to
GjTMCR7 (j=0,1), GiTPR6, GiTPR7, GjTM0 to GjTM7, GiPOCR0 to GiPOCR7, GiPO0 to GiPO7, G3MK4
to G3MK7, GjFS, GiFE, G2RTP, and G3RTP registers are affected by the count source (f
BCK1 to BCK0 bits in the GiBCR0 register.
Set the BCK1 to BCK0 bits before setting the GiBT, GiBCR1, BTSR, GjTMCR0 to GjTMCR7, GiTPR6,
GiTPR7, GjTM0 to GjTM7, GiPOCR0 to GiPOCR7, GiPO0 to GiPO7, G3MK4 to G3MK7, GjFS, GiFE,
G2RTP, and G3RTP registers.
Operations controlled by the values written to the GjRI, GjTO, GiCR, GiRB, GiMR, GjEMR, GjETC,
GjERC, GjIRF, GiTB, GjCMP0 to GjCMP3, GjMSK0, GjMSK1, GjTCRC, GjRCRC, IECR, IEAR, IETIF,
IERIF, and G3FLG registers are affected by the transfer clock. Set transfer clock before setting the GjRI,
GjTO, GiCR, GiRB, GiMR, GjEMR, GjETC, GjERC, GjIRF, GiTB, GjCMP0 to GjCMP3,
GjMSK0,GjMSK1, GjTCRC, GjRCRC, IECR, IEAR, IETIF, IERIF, and G3FLG registers.
The BTSR register is a located in the intelligent I/O group 2. When starting the base timer using the BTiS
bit in the BTSR register, set the BTiS bit to "1" (base timer starts counting) after selecting the count source
for the intelligent I/O group 2. If the BTiS bit is not being used, set the BTiS bit to "0" (base timer reset)
after selecting the count source for the intelligent I/O group 2.
Set only either the BTiS bit or the BTS bit in the GiBCR1 register to "1" when starting the base timer. If
both BTiS bit and the BTS bit are set to "0", both bits must be set "0" when stopping the base timer.
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27. Precautions (Intelligent I/O)
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