M30833FJGP#U3 Renesas Electronics America, M30833FJGP#U3 Datasheet - Page 238

• Manufacturer Part Number: M30833FJGP#U3
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 87
• Interface Type: UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
. v
J
Table 16.29 Clock-Divided Synchronous Function Select
Figure 16.27 Clock-Divided Synchronous Function
2
0
i=0 to 4
1
9
C
SCLKDIV Bit in
UiSMR Register
3 .
B
8 /
To generate the internal clock synchronized with the external clock, first set the SU1HIM bit in the
UiSMR2 register (i=0 to 4) and the SCLKDIV bit in the UiSMR register to values shown in Table 16.29.
Then apply a trigger signal to the CTSi pin. Either the same clock cycle as the external clock or external
clock divided by two can be selected as the transfer clock. The SCLKSTPB bit in the UiC1 register
controls the transfer clock. Set the SCLKSTPB bit accordingly, to start or stop the transfer clock during an
external clock operation. Figure 16.27 shows an example of the clock-divided synchronous function.
0
1
3
0
A
B
3
J
G
4
0
0
1
a
Trigger Signal
from the CTSi Pin
External Clock
from the CLKi Pin
0 -
n
o r
3 .
1
TxDi
TxDi
u
Transfer Clock
Transfer Clock
, 1
3
p
1
2
(
i=0 to 4
A, B : See Table 16.29.
M
0
0
3
6
2
C
UiSMR2 Register
Page 213
8 /
SU1HIM Bit in
0 or 1
, 3
0
1
M
3
2
C
f o
8 /
4
1
3
8
) T
8
1
2
Not synchronized
Same division as the external clock
Same division as the external clock
divided by 2
1
2
3
Clock-Divided Synchronous Function
3
4
2
4
5
5
6
3
6
7
7
8
4
8
5
The SCLKSTPB bit in the UiC1 register
stops the clock
16. Serial I/O (Special Function)
6
-
A in Figure 16.27
B in Figure 16.27
Example of Waveform
7
8