M30833FJGP#U3 Renesas Electronics America, M30833FJGP#U3 Datasheet - Page 274

• Manufacturer Part Number: M30833FJGP#U3
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 87
• Interface Type: UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
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J
2
Figure 21.1 Intelligent I/O Group 0 Block Diagram
0
1
C
9
Figures 21.1 to 21.4 show block diagram of the intelligent I/O groups 0 to 3.
3 .
B
8 /
0
1
NOTES:
3
0
3
(Note 1)
1. These pins are not connected to external pins in the 100-pin package.
2. Each register enters a reset state after the G0BCR0 register supplies the
3. See Figure 10.14.
J
G
4
a
clock.
Two-phase
pulse signal
is applied
0 -
f
n
o r
1
G0RI register
3 .
Receive
Receive
1
External clock
External clock
register
u
buffer
, 1
3
p
1
ch0
ch3
ch1
ch2
ch3
2
(
INPC0
INPC0
INPC0
M
/ ISCLK0
/ ISRxD0
0
selector
selector
INPC0
INPC0
INPC0
INPC0
INPC0
Clock
Clock
BCK1 to BCK0
11
10
0
3
6
Receive operation clock
2
0
1
2
1
3
4
5
6
7
C
RXSL
Transmit
operation clock
0
Page 249
8 /
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
filter
filter
filter
filter
filter
filter
filter
filter
, 3
BT0S
BTS
M
10 : f
11 : f
10 : f
11 : f
10 : f
11 : f
10 : f
11 : f
10 : f
11 : f
10 : f
11 : f
10 : f
11 : f
10 : f
11 : f
Polarity
inverse
IPOL
3
BT0
1
BT0
1
BT0
1
BT0
1
BT0
1
BT0
1
BT0
1
BT0
1
2
C
f o
00
00
00
00
00
00
00
00
8 /
Request from the INT pin
Request from the group1
4
3
DIV4 to DIV0
CTS1 to CTS0
CTS1 to CTS0
CTS1 to CTS0
CTS1 to CTS0
CTS1 to CTS0
CTS1 to CTS0
CTS1 to CTS0
CTS1 to CTS0
8
G0CMP3 register
(Receive data register)
select
select
select
select
select
select
select
(Transmit buffer register)
by 2(n+1)
Edge
Edge
Edge
Edge
Edge
Edge
Edge
select
) T
Edge
8
Divider
G0CMP3 register
G0DR register
G0CMP3 register
G0TB register
register
register
Reset
Clock wait
Buffer
G0CMP3 register
Transmit
Transmit
Shift
register
control
circuit
buffer
function
function
Gate
Gate
1
1
GT
GT
0
0
Request by matching the base timer with the G0PO0 register
Prescaler
Prescaler
function
function
DIV4 to DIV0 bits, BCK1 to BCK0 bits : Bits in the G0BCR0 register
BTS : Bit in the G0BCR1 register
BT0S : Bit in BTSR register
CTS1 to CTS0, DF1 to DF0, GT, PR : Bits in the G0TMCRj register (j = 0 to 7)
MOD2 to MOD0 : Bits in the G0POCRj register
TXSL, RXSL : Bits in the G0EMR register
OPOL, IPOL : Bits in the G0CR register
f
BT0
G0RCRC
generation circuit
generation circuit
generation circuit
register
Bit insert circuit
Transmit latch
Bit insert
Start bit
Stop bit
Start bit
Stop bit
check
check
check
1
1
SOF
Group0 base timer reset
PR
PR
0
0
Comparator
Comparator
Arbitration
generation circuit
Comparator
Receive data
Comparator
G0TM0, G0PO0
register
G0TM1, G0PO1
register
G0TM2, G0PO2
register
G0TM3, G0PO3
register
G0TM4, G0PO4
register
G0TM5, G0PO5
register
G0TM6, G0PO6
register
selector
Data
generation circuit
selector
Transmit data
Data
Base timer
G0TCRC
register
interrupt
Special
G0TO register
G0RB register
Base timer interrupt request
Overflow of base timer bit 15
check
Transmission
TXSL
Transmit
Transmit
Receive
Receive
register
register
buffer
buffer
Reception
PWM
output
output
output
PWM
PWM
1
0
Polarity
OPOL
inverse
000 to 010
000 to 010
111
Waveform generation match
signal for group1
(For cascaded connection)
Time measurement trigger
for the group1
(For cascaded connection)
Ch0 to ch7
interrupt request signal
(3)
OUTC0
OUTC0
MOD2 to MOD0
(SIO0TR)
(G0TOR)
Transmit interrupt request
HDLC data transmit
interrupt request
(SIO0RR)
Receive interrupt request
(SRT0R)
(G0RIR)
HDLC data receive
interrupt request
Special communication
interrupt request
MOD2 to MOD0
111
4
5
OUTC0
(3)
(3)
(3)
OUTC0
(3)
(3)
(Note 1)
21. Intelligent I/O
1
/ISCLK0
0
/ISTxD0