R5F21191SP#U0 Renesas Electronics America, R5F21191SP#U0 Datasheet - Page 98

IC R8C MCU FLASH 8K 20SSOP

R5F21191SP#U0

Manufacturer Part Number
R5F21191SP#U0
Description
IC R8C MCU FLASH 8K 20SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/19r
Datasheets

Specifications of R5F21191SP#U0

Core Processor
R8C
Core Size
16-Bit
Speed
20MHz
Connectivity
SIO, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
13
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x1b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-SSOP
For Use With
R0K521134S000BE - KIT EVAL STARTER FOR R8C/13R0E521174CPE10 - EMULATOR COMPACT R8C/18/19/1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
R8C/18 Group, R8C/19 Group
Rev.1.30
REJ09B0222-0130
Figure 12.6
Table 12.5
Watchdog timer, oscillation stop detection, voltage monitor 2
Software, address match, single-step, address break
12.1.6.5
12.1.6.6
Figure 12.6 shows the Interrupt Response Time. The interrupt response time is the period between
an interrupt request generation and the execution of the first instruction in the interrupt routine. The
interrupt response time includes the period between interrupt request generation and the completion
of execution of the instruction (refer to (a) in Figure 12.6) and the period required to perform the
interrupt sequence (20 cycles, refer to (b) in Figure 12.6).
When an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the
acknowledged interrupt is set in the IPL.
When a software interrupt or special interrupt request is acknowledged, the level listed in Table 12.5
is set in the IPL. Table 12.5 lists the IPL Value When Software or Special Interrupt Is Acknowledged.
Apr 14, 2006
Interrupt request is generated. Interrupt request is acknowledged.
Interrupt Response Time
IPL Change when Interrupt Request is Acknowledged
IPL Value When Software or Special Interrupt Is Acknowledged
Interrupt Response Time
(a) Period between interrupt request generation and the completion of execution of an
(b) 21 cycles for address match and single-step interrupts.
Interrupt Source
instruction. The length of time varies depending on the instruction being executed. The
DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a
register is set as the divisor).
Page 81 of 233
Instruction
(a)
Interrupt response time
Interrupt sequence
20 cycles (b)
interrupt routine
Instruction in
Value Set in IPL
Not changed
7
Time
12. Interrupts

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