MC9S08LC36LH Freescale Semiconductor, MC9S08LC36LH Datasheet - Page 149

• Manufacturer Part Number: MC9S08LC36LH
• Description: IC MCU 36K FLASH 2K RAM 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08LC36LH

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 36KB (36K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 2x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: S08LC
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2.5 KB
• Interface Type: I2C/SCI/SPI1/SPI2
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 18
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2-ch x 12-bit
• For Use With: DEMO9S08LC60 - BOARD DEMO FOR 9S08LC60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.4.2
For a segment on the LCD panel to be displayed, data must be written to the LCDRAM registers. Each bit
in the LCDRAM registers correspond to a segment on the LCD panel.
The LCDRAM registers provide access to two different register groups depending on the state of the
LCDDRMS bit in the LCDCMD register. If LCDDRMS = 0, the LCDRAM register accesses a register
bank that controls the on/off state for frontplane drivers
accesses a register bank that enables the blink mode for each individual LCD segment
If LCDDRMS = 0, when the LCDEN bit is set and the corresponding FP[31:0]EN bit is set, writing a 1 to
a given LCDRAM location will result in the corresponding display segment being driven with a
differential root mean square (RMS) voltage necessary to turn the segment on.Writing a 0 to a given
location will result in the corresponding display segment being driven with a differential RMS voltage
necessary to turn the segment off.
The LCDRAM is a dual port RAM that interfaces with the internal address and data buses of the MCU.
When LCDEN = 0, the LCDRAM registers can be used as on-chip RAM. Writing or reading of the
LCDEN bit does not change the contents of the LCDRAM registers.After a reset, the LCDRAM contents
will be indeterminate.
9.4.2.1
The LCD module data register clear command deasserts all accessible bits in the LCDRAM registers.
LCDDRMS bit in the LCDCMD register determines which LCDRAM registers bits are accessible.To
clear all LCD segment blink enables in the LCDRAM registers, the LCDCLR bit must be asserted only
when the LCDDRMS bit is asserted. To clear the entire LCD display, the LCDCLR bit must be asserted
only when the LCDDRMS bit is deasserted.
9.4.2.2
The LCD module display blank command clears all segments in the LCD display regardless of the contents
of the LCDRAM registers or the state of the LCDDRMS bit. This bit does not disable the LCD module
timing generator. Writing or reading of the BLANK bit does not change the contents of the LCDRAM
registers.
9.4.3
The LCD module LCD panel blink capabilities are very flexible. The LCD module can be configured to
blink either individual LCD segments or the entire LCD panel. The blink rate frequency is configured
using the BRATE[2:0] bit field.
The LCD will blink at the configured frequency while the BLINK bit in the LCDBCTL register is set to 1.
When the BLINK bit is modified to start or stop the LCD display blinking, the BLINK command change
takes place at the beginning of the next LCD frame cycle.
Freescale Semiconductor
LCDRAM Registers
LCD Blinking
LCDRAM Data Clear Command
LCDRAM Data Blank Command
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
.
If LCDDRMS = 1, the LCDRAM register bank
Chapter 9 Liquid Crystal Display Driver (S08LCDV1)
.
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