MC9S08LC36LH Freescale Semiconductor, MC9S08LC36LH Datasheet - Page 90

• Manufacturer Part Number: MC9S08LC36LH
• Description: IC MCU 36K FLASH 2K RAM 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08LC36LH

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 36KB (36K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 2x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: S08LC
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2.5 KB
• Interface Type: I2C/SCI/SPI1/SPI2
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 18
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2-ch x 12-bit
• For Use With: DEMO9S08LC60 - BOARD DEMO FOR 9S08LC60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 6 Parallel Input/Output
6.2.4.3
An output pin can be selected to have high output drive strength by setting the corresponding bit in the
drive strength select register (PTBDSn). When high drive is selected a pin is capable of sourcing and
sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that
the total current source and sink limits for the chip are not exceeded. Drive strength selection is intended
to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin
to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load.
Because of this the EMC emissions may be affected by enabling pins as high drive.
6.2.5
This section provides information about all registers and control bits associated with the parallel I/O ports.
The parallel I/O registers are located in page zero of the memory map.
Refer to tables in
This section refers to registers and control bits only by their names. A Freescale-provided equate or header
file normally is used to translate these names into the appropriate absolute addresses.
90
PTBDS[7:0]
Reset
Field
7:0
W
R
PTBDS7
Port C Registers
Output Drive Strength Select (
Output Drive Strength Selection for Port B Bits—Each of these control bits selects between low and high output
drive for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port B bit n.
1 High output drive strength selected for port B bit n.
0
7
Chapter 4,
PTBDS6
Figure 6-17. Drive Strength Selection for Port B (PTBDS)
0
6
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
“Memory” for the absolute address assignments for all parallel I/O registers.
Table 6-10. PTBDS Field Descriptions
PTBDS5
0
5
PTBDS4
0
4
PTBDS)
Description
PTBDS3
3
0
PTBDS2
0
2
PTBDS1
Freescale Semiconductor
0
1
PTBDS0
0
0