MC9S08LC36LH Freescale Semiconductor, MC9S08LC36LH Datasheet - Page 88

• Manufacturer Part Number: MC9S08LC36LH
• Description: IC MCU 36K FLASH 2K RAM 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08LC36LH

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 36KB (36K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 2x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: S08LC
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2.5 KB
• Interface Type: I2C/SCI/SPI1/SPI2
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 18
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2-ch x 12-bit
• For Use With: DEMO9S08LC60 - BOARD DEMO FOR 9S08LC60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
Chapter 6 Parallel Input/Output
6.2.3.2
6.2.4
Associated with the parallel I/O ports is a set of registers located in the high page register space that operate
independently of the parallel I/O registers. These registers are used to control pullups, slew rate, and drive
strength for the associated pins and may be used in conjunction with the peripheral functions on these pins
for most modules.
The pins associated with Port B are controlled by the registers in this section. These registers control the
pin pullup, slew rate and drive strength of the Port B pins independent of the parallel I/O registers.
6.2.4.1
An internal pullup device can be enabled for each port pin by setting the corresponding bit in the pullup
enable register (PTBPEn). The pullup device is disabled if the pin is configured as an output by the parallel
I/O control logic or any shared peripheral function regardless of the state of the corresponding pullup
enable register bit. The pullup device is also disabled if the pin is controlled by an analog function.
88
PTBDD[7:0]
PTBDD2 has no effect on the output-only PTB2 pin.
Reset
Field
7:0
W
R
PTBDD7
Port B Control Registers
Port B Data Direction Registers (PTBDD)
Internal Pullup Enable (
Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for
PTBD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn.
0
7
PTBDD6
0
6
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Figure 6-13. Data Direction for Port B (PTBDD)
Table 6-7. PTBDD Field Descriptions
PTBDD5
0
5
PTBPE)
PTBDD4
0
4
Description
PTBDD3
3
0
PTBDD2
0
2
1
PTBDD1
Freescale Semiconductor
0
1
PTBDD0
0
0