DF2266TF13V Renesas Electronics America, DF2266TF13V Datasheet - Page 113
DF2266TF13V
Manufacturer Part Number
DF2266TF13V
Description
IC H8S/2266 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2266TF20V.pdf
(712 pages)
Specifications of DF2266TF13V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 113 of 712
- Download datasheet (5Mb)
Notes: 1. Lower 16 bits of the address.
4.3
A reset has the highest exception priority.
When the RES pin goes low, all processing halts and this LSI enters the reset. A reset initializes
the internal state of the CPU and the registers of on-chip peripheral modules. The interrupt control
mode is 0 immediately after reset.
When the RES pin goes high from the low state, this LSI starts reset exception handling.
The chip can also be reset by overflow of the watchdog timer. For details see section 12,
Watchdog Timer (WDT).
4.3.1
When the RES pin goes low, this LSI enters the reset. To ensure that this LSI is reset, hold the
RES pin low for at least 20 ms at power-up. To reset the chip during operation, hold the RES pin
low for at least 20 states. When the RES pin goes high after being held low for the necessary time,
this LSI starts reset exception handling as follows.
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
2. The reset exception handling vector address is read and transferred to the PC, and program
Note: * Supported only by the H8S/2268 Group.
Exception Source
Internal interrupt *
External interrupt WKP0 to WKP7
Internal interrupt
initialized, the T bit in EXR * is cleared to 0, and the I bits in EXR * and CCR is set to 1.
execution starts from the address indicated by the PC.
2. For details of internal interrupt vectors, see section 5.4.3, Interrupt Exception Handling
3. For details on direct transitions, see section 22.10, Direct Transitions.
4. Supported only by the H8S/2268 Group.
Reset
Reset Exception Handling
Vector Table.
2
Vector Number
24
107
120
123
108
⎜
⎜
Rev. 5.00 Sep. 01, 2009 Page 61 of 656
Vector Address Advanced Mode *
H'0060 to H'0063
H'01AC to H'01AF
H'01B0 to H'01B3
H'01E0 to H'01E3
H'01EC to H'01EF
⎜
⎜
Section 4 Exception Handling
REJ09B0071-0500
1
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