DF2266TF13V Renesas Electronics America, DF2266TF13V Datasheet - Page 594
DF2266TF13V
Manufacturer Part Number
DF2266TF13V
Description
IC H8S/2266 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2266TF20V.pdf
(712 pages)
Specifications of DF2266TF13V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 21 Clock Pulse Generator
Rev. 5.00 Sep. 01, 2009 Page 542 of 656
REJ09B0071-0500
5
Bit
4
3
2
Bit Name
NESEL
SUBSTP
RFCUT
⎯
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Noise Elimination Sampling Frequency Select
This bit selects the sampling frequency of the subclock
(φ
the clock (φ) generated by the system clock oscillator
Set 0 when φ is 5 MHz or higher. Set 1 when φ is 2.1 MHz
or lower. Any value can be set when φ is 2.1 to 5 MHz.
0: Sampling using 1/32 × φ
1: Sampling using 1/4 × φ
Subclock Enable
This bit enables/disables subclock generation. This bit
should be set to 1 when subclock is not used.
0: Enables subclock generation.
1: Disables subclock generation.
Oscillation Circuit Feedback Resistance Control Bit
Selects whether or not built-in feedback resistance and
duty adjustment circuit of the system clock generator are
used when an external clock is input. Do not access
when the crystal resonator is used.
After setting this bit in the external clock input state, enter
software standby mode, watch mode, or subactive mode.
When software standby mode, watch mode, or subactive
mode is entered, switch whether or not built-in feedback
resistance and duty adjustment circuit are used.
0: Built-in feedback resistance and duty adjustment circuit
1: Built-in feedback resistance and duty adjustment circuit
Reserved
This is a readable/writable bit, but the write value should
always be 0.
SUB
of the system clock generator used.
of the system clock generator not used.
) generated by the subclock oscillator is sampled by
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