DF2266TF13V Renesas Electronics America, DF2266TF13V Datasheet - Page 291
![IC H8S/2266 MCU FLASH 100-TQFP](/photos/12/29/122926/df2266tf13v_sml.jpg)
DF2266TF13V
Manufacturer Part Number
DF2266TF13V
Description
IC H8S/2266 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2266TF20V.pdf
(712 pages)
Specifications of DF2266TF13V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is
set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare
match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The
H8S/2268 Group TPU has eight input capture/compare match interrupts and the H8S/2264 Group
TPU has four input capture/compare match interrupts, four for channel 0, and two each for
channels 1 and 2.
Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the
TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt
request is cleared by clearing the TCFV flag to 0. The H8S/2268 Group TPU has three overflow
interrupts and the H8S/2264 Group TPU has two overflow interrupts, one for each channel
(channels 0 to 2, or 1 and 2).
Underflow Interrupt (H8S/2268 Group Only): An interrupt is requested if the TCIEU bit in
TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a
channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has two
underflow interrupts, one each for channels 1 and 2.
10.7
The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For
details, see section 8, Data Transfer Controller (DTC).
A total of eight TPU input capture/compare match interrupts can be used as DTC activation
sources, four for channel 0, and two each for channels 1 and 2.
10.8
The A/D converter can be activated by the TGRA input capture/compare match for a channel.
If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a
TGRA input capture/compare match on a particular channel, a request to begin A/D conversion is
sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D
converter side at this time, A/D conversion is begun.
In the H8S/2268 Group TPU, a total of three TGRA input capture/compare match interrupts can
be used as A/D converter conversion start sources, one for each channel (channels 0 to 2). While
in the H8S/2264 Group TPU, a total of two TGRA input capture/compare match interrupts can be
used, one for each channel (channels 1 and 2).
DTC Activation (H8S/2268 Group Only)
A/D Converter Activation
Rev. 5.00 Sep. 01, 2009 Page 239 of 656
Section 10 16-Bit Timer Pulse Unit (TPU)
REJ09B0071-0500
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