M30833FJFP#U5 Renesas Electronics America, M30833FJFP#U5 Datasheet - Page 125

• Manufacturer Part Number: M30833FJFP#U5
• Description: IC M32C/83 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJFP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
. v
J
Figure 10.6 Interrupt Response Time
2
0
10.6.4 Interrupt Response Time
1
9
C
3 .
B
Figure 10.6 shows an interrupt response time. Interrupt response time is the period between an interrupt
generation and the execution of the first instruction in an interrupt service routine. An interrupt response
time includes the period between an interrupt request generation and the completed execution of an in-
struction ((a) in Figure 10.6) and the period required to perform an interrupt sequence ((b) in Figure 10.6).
8 /
Time (a) varies depending on the instruction being executed. The DIV instruction requires the longest
time (a); 40 cycles when an immediate value or register is set as the divisor .
When the divisor is a value in the memory, the following value is added.
X is the number of wait states for a divisor space. Y is the number of wait states for the space that stores
indirect addresses. If X and Y are in an odd address or in 8-bit bus space, the X and Y value must be
doubled.
Table 10.4 lists time (b).
0
1
3
0
3
J
G
4
a
Interrupt request is generated
0 -
n
o r
(a) Period between an interrupt request generation and the completed execution of an instruction.
(b) Period required to perform an interrupt sequence.
3 .
1
u
, 1
3
p
1
2
(
M
0
0
• Normal addressing
• Index addressing
• Indirect addressing
• Indirect index addressing
3
6
2
C
8 /
Page 100
, 3
M
3
2
C
Instruction
f o
8 /
4
3
8
Interrupt response time
) T
8
(a)
Interrupt request is acknowledged
Interrupt sequence
: 2 + X
: 3 + X
: 5 + X + 2Y
: 6 + X + 2Y
(b)
Instruction in an
interrupt routine
Time
10. Interrupts