M30833FJFP#U5 Renesas Electronics America, M30833FJFP#U5 Datasheet - Page 292

• Manufacturer Part Number: M30833FJFP#U5
• Description: IC M32C/83 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJFP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
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J
2
Figure 21.19 Counter Increment/ Decrement Mode (Group 0 and 1)
0
1
C
9
3 .
B
8 /
(1) When the IT bit in the GiBCR0 register (i= 0 to 1) is set to "0" (bit 15 in the base timer overflows)
(2) When the IT bit in the GiBCR0 register (i= 0 to 1) is set to "1" (bit 14 in the base timer overflows)
(3) When the RST1 bit in the GiBCR1 register (i= 0 to 1) is set to "1" (the base timer is reset by matching with the GiPO0 register)
0
1
3
0
BTkR bit in IIOjIR register
BTkR bit in IIOjIR register
3
J
G
4
a
0 -
n
o r
b15 overflow signal
3 .
Base Timer i
Base Timer i
Base Timer i
1
u
b14 overflow signal
, 1
3
p
1
j=4, 7, 8, 11; k=0 to 3
The above applies under the following conditions:
• The RST1 in the GiBCR1 register is set to "0" (the base timer is not reset by matching the GiPO0 register).
• The UD1 to UD0 bits in the GiBCR1 register are set to "01
j=4, 7, 8, 11; k=0 to 3
The above applies under the following conditions:
• Value of GiPO0 register: "8000
• The UD1 to UD0 bits in the GiBCR1 register are set to "01
2
(
M
j=4, 7, 8, 11; k=0 to 3
The above applies under the following conditions:
• The RST1 in the GiBCR1 register is set to "0" (the base timer is not reset by matching the GiPO0 register).
• The UD1 to UD0 bits in the GiBCR1 register are set to "01
0
0
3
6
2
C
4000
8000
8 /
C000
Page 267
FFFF
0000
8000
FFFF
8002
8000
0000
, 3
16
16
16
16
16
16
"1"
"1"
"0"
"0"
M
16
16
16
16
"1"
"0"
"1"
"0"
3
2
C
f o
8 /
4
3
8
) T
8
16
"
2
2
" (counter increment/decrement mode).
" (counter increment/decrement mode).
2
" (counter increment/decrement mode).
Write "0" by program
if setting to "0"
Write "0" by program
if setting to "0"
21. Intelligent I/O (Base Timer)