ATTINY26L-8SU Atmel, ATTINY26L-8SU Datasheet - Page 73

• Manufacturer Part Number: ATTINY26L-8SU
• Description: ID MCU AVR 2K 5V 8MHZ 20-SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY26L-8SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Package: 20SOIC
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 16
• Interface Type: SPI/USI
• On-chip Adc: 11-chx10-bit
• Number Of Timers: 2
• Cpu Family: ATtiny
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 128Byte
• # I/os (max): 16
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: SOIC
• Processor Series: ATTINY2x
• Core: AVR8
• Data Ram Size: 128 B
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATTINY26L-8SJ; ATTINY26L-8SJ

Timer/Counter1
Output Compare
RegisterB – OCR1B
Timer/Counter1
Output Compare
RegisterC – OCR1C
PLL Control and
Status Register –
PLLCSR
1477K–AVR–08/10
A compare match will set the compare interrupt flag OCF1A after a synchronization delay follow-
ing the compare event.
The Output Compare Register B is an 8-bit read/write register.
The Timer/Counter Output Compare Register B contains data to be continuously compared with
Timer/Counter1. Actions on compare matches are specified in TCCR1A. A compare match does
only occur if Timer/Counter1 counts to the OCR1B value. A software write that sets TCNT1 and
OCR1B to the same value does not generate a compare match.
A compare match will set the compare interrupt flag OCF1B after a synchronization delay follow-
ing the compare event.
The Output Compare Register C is an 8-bit read/write register.
The Timer/Counter Output Compare Register C contains data to be continuously compared with
Timer/Counter1. A compare match does only occur if Timer/Counter1 counts to the OCR1C
value. A software write that sets TCNT1 and OCR1C to the same value does not generate a
compare match.
If the CTC1 bit in TCCR1B is set, a compare match will clear TCNT1 and set an Overflow Inter-
rupt Flag (TOV1). The flag is set after a synchronization delay following the compare event.
This register has the same function in normal mode and PWM mode.
• Bit 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
• Bit 2 – PCKE: PCK Enable
The PCKE bit change the Timer/Counter1 clock source. When it is set, the asynchronous clock
mode is enabled and fast 64 MHz PCK clock is used as Timer/Counter1 clock source. If this bit
is cleared, the synchronous clock mode is enabled, and system clock CK is used as
Timer/Counter1 clock source. This bit can be set only if PLLE bit is set. It is safe to set this bit
only when the PLL is locked i.e., the PLOCK bit is 1.
• Bit 1 – PLLE: PLL Enable
When the PLLE is set, the PLL is started and if needed internal RC Oscillator is started as a PLL
reference clock. If PLL is selected as a system clock source the value for this bit is always 1.
• Bit 0 – PLOCK: PLL Lock Detector
Bit
$2C ($4C)
Read/Write
Initial Value
Bit
$2B ($4B)
Read/Write
Initial Value
Bit
$29 ($29)
Read/Write
Initial Value
MSB
MSB
R/W
R/W
R
7
0
7
0
7
–
0
R/W
R/W
R
6
0
6
0
6
–
0
R/W
R/W
R
5
0
5
0
5
–
0
R/W
R/W
R
4
0
4
0
4
–
0
R/W
R/W
R
3
0
3
0
3
–
0
PCKE
R/W
R/W
R/W
2
0
2
0
2
0
PLLE
R/W
R/W
R/W
0/1
1
0
1
0
1
PLOCK
LSB
LSB
R/W
R/W
R
0
0
0
0
0
0
PLLCSR
OCR1B
OCR1C
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