ATTINY26L-8SU Atmel, ATTINY26L-8SU Datasheet - Page 89
![ID MCU AVR 2K 5V 8MHZ 20-SOIC](/photos/6/80/68042/453-20-soic_sml.jpg)
ATTINY26L-8SU
Manufacturer Part Number
ATTINY26L-8SU
Description
ID MCU AVR 2K 5V 8MHZ 20-SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY26L-8SU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Package
20SOIC
Device Core
AVR
Family Name
ATtiny
Maximum Speed
8 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
16
Interface Type
SPI/USI
On-chip Adc
11-chx10-bit
Number Of Timers
2
Cpu Family
ATtiny
Device Core Size
8b
Frequency (max)
8MHz
Total Internal Ram Size
128Byte
# I/os (max)
16
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
20
Package Type
SOIC
Processor Series
ATTINY2x
Core
AVR8
Data Ram Size
128 B
Maximum Clock Frequency
8 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATTINY26L-8SJ
ATTINY26L-8SJ
ATTINY26L-8SJ
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY26L-8SU
Manufacturer:
Atmel
Quantity:
3 500
Part Number:
ATTINY26L-8SU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
1477K–AVR–08/10
Figure 48. Two-wire Mode, Typical Timing Diagram
Referring to the timing diagram (Figure 48.), a bus transfer involves the following steps:
1. The a start condition is generated by the master by forcing the SDA low line while the
2. In addition, the start detector will hold the SCL line low after the master has forced an
3. The master set the first bit to be transferred and releases the SCL line (C). The slave
4. After eight bits are transferred containing slave address and data direction (read or
5. If the slave is addressed it holds the SDA line low during the acknowledgment cycle
6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is given
If the slave is not able to receive more data it does not acknowledge the data byte it has last
received. When the master does a read operation it must terminate the operation by force the
acknowledge bit low after the last byte transmitted.
Figure 49. Start Condition Detector, Logic Diagram
SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift
Register, or by setting the PORTB0 bit to zero. Note that DDRB0 must be set to one for
the output to be enabled. The slave device’s start detector logic (Figure 49.) detects the
start condition and sets the USISIF flag. The flag can generate an interrupt if necessary.
negative edge on this line (B). This allows the slave to wake up from sleep or complete
its other tasks, before setting up the Shift Register to receive the address by clearing the
start condition flag and reset the counter.
samples the data and shift it into the serial register at the positive edge of the SCL clock.
write), the slave counter overflows and the SCL line is forced low (D). If the slave is not
the one the master has addressed it releases the SCL line and waits for a new start
condition.
before holding the SCL line low again (i.e., the Counter Register must be set to 14 before
releasing SCL at (D)). Depending of the R/W bit the master or slave enables its output. If
the bit is set, a master read operation is in progress (i.e., the slave drives the SDA line)
The slave can hold the SCL line low after the acknowledge (E).
by the master (F). Or a new start condition is given.
SDA
SCL
Write( USISIF)
A B
S
C
ADDRESS
SDA
SCL
1 - 7
R/W
8
D
ACK
9
E
DATA
1 - 8
D Q
CLR
ACK
9
D Q
CLR
DATA
1 - 8
USISIF
CLOCK
HOLD
ACK
9
P
F
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